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a54c207c37
MISRA Advisory Rule states that the precedence of operators within expressions should be made explicit. This change removes the Advisory Rule 12.1 violations from hal code. Jira NVGPU-3178 Change-Id: If903544e1aa7264dc07f959a65ff666dfe89a230 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277478 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include "hal/fifo/pbdma_gm20b.h"
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#include "channel_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
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void gk20a_channel_enable(struct nvgpu_channel *ch)
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{
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nvgpu_writel(ch->g, ccsr_channel_r(ch->chid),
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gk20a_readl(ch->g, ccsr_channel_r(ch->chid)) |
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ccsr_channel_enable_set_true_f());
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}
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void gk20a_channel_disable(struct nvgpu_channel *ch)
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{
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nvgpu_writel(ch->g, ccsr_channel_r(ch->chid),
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gk20a_readl(ch->g,
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ccsr_channel_r(ch->chid)) |
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ccsr_channel_enable_clr_true_f());
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}
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/* ccsr_channel_status_v is four bits long */
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static const char * const ccsr_chan_status_str[] = {
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"idle",
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"pending",
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"pending_ctx_reload",
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"pending_acquire",
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"pending_acq_ctx_reload",
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"on_pbdma",
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"on_pbdma_and_eng",
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"on_eng",
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"on_eng_pending_acquire",
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"on_eng_pending",
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"on_pbdma_ctx_reload",
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"on_pbdma_and_eng_ctx_reload",
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"on_eng_ctx_reload",
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"on_eng_pending_ctx_reload",
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"on_eng_pending_acq_ctx_reload",
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"N/A",
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};
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void gk20a_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
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struct nvgpu_channel_hw_state *state)
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{
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u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid));
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u32 status_v = ccsr_channel_status_v(reg);
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state->next = ccsr_channel_next_v(reg) == ccsr_channel_next_true_v();
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state->enabled = ccsr_channel_enable_v(reg) ==
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ccsr_channel_enable_in_use_v();
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state->ctx_reload =
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(status_v ==
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ccsr_channel_status_pending_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_pending_acq_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_on_pbdma_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_on_eng_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_on_eng_pending_ctx_reload_v()) ||
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(status_v ==
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ccsr_channel_status_on_eng_pending_acq_ctx_reload_v());
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state->busy = ccsr_channel_busy_v(reg) == ccsr_channel_busy_true_v();
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state->pending_acquire =
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(status_v == ccsr_channel_status_pending_acquire_v()) ||
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(status_v == ccsr_channel_status_on_eng_pending_acquire_v());
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state->status_string = ccsr_chan_status_str[status_v];
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}
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