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fdd768a302
Patch adds a BUG() in the gm20b_fuse_status_opt_tpc_gpc() if input gpc is more than max gpc count. Jira NVGPU-6410 Change-Id: Iefd346bcf8865b831543e6fe389c63a79f3653ec Signed-off-by: Prateek sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548477 (cherry picked from commit bc8fd66432ee8369324de7371d1683336b6f896e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552296 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/*
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* GM20B FUSE
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*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/fuse.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "fuse_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
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u32 gm20b_fuse_status_opt_fbio(struct gk20a *g)
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{
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return nvgpu_readl(g, fuse_status_opt_fbio_r());
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}
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u32 gm20b_fuse_status_opt_fbp(struct gk20a *g)
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{
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return nvgpu_readl(g, fuse_status_opt_fbp_r());
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}
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u32 gm20b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp)
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{
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return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
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}
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u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
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{
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u32 max_gpc_count = g->ops.top.get_max_gpc_count(g);
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if (gpc >= max_gpc_count) {
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BUG();
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}
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return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
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}
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void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val)
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{
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nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val);
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}
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u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g)
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{
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return nvgpu_readl(g, fuse_opt_sec_debug_en_r());
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}
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u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g)
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{
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return nvgpu_readl(g, fuse_opt_priv_sec_en_r());
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}
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