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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "hal/gr/ecc/ecc_gv11b.h"
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#include "ecc_ga10b.h"
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#include <nvgpu/hw/ga10b/hw_gr_ga10b.h>
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static inline u32 pri_gpc0_mmu0_l1tlb_ecc_control_r(void)
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{
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return gr_gpc0_mmu0_l1tlb_ecc_control_r();
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}
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static inline u32 pri_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(u32 v)
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{
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return gr_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f(v);
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}
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struct nvgpu_hw_err_inject_info mmu_ecc_err_desc[] = {
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/*
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* NV_SCAL_LITTER_NUM_GPCMMU_PER_GPC only shows 1 GPCMMU per GPC.
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* Add support to GPC_MMU0_L1TLB, GPC_MMU L1TLB not handled here.
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*/
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NVGPU_ECC_ERR("l1tlb_sa_data_ecc_uncorrected",
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gv11b_gr_intr_inject_mmu_ecc_error,
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pri_gpc0_mmu0_l1tlb_ecc_control_r,
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pri_gpc0_mmu0_l1tlb_ecc_control_inject_uncorrected_err_f),
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};
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struct nvgpu_hw_err_inject_info_desc mmu_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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ga10b_gr_ecc_get_mmu_err_desc(struct gk20a *g)
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{
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mmu_err_desc.info_ptr = mmu_ecc_err_desc;
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mmu_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(mmu_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &mmu_err_desc;
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}
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