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1182a49f5c
For gv11b, priv ring interrupts were not triggered for PLM L2 registers. So, read back was implemented to confirm data written to L2 registers. Verified that LTC registers are not PLM protected, and read back implemented after write is not necessary. Replace nvgpu_writel_check with nvgpu_writel. Bug 200625897 Bug 2989973 Jira NVGPU-5490 Change-Id: Ie0815899589c506e13ab2f9342657cb4d68b8fc8 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2363384 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/*
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* GP10B L2
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/ltc.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/hw/gp10b/hw_ltc_gp10b.h>
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#include "ltc_gm20b.h"
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#include "ltc_gp10b.h"
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u64 gp10b_determine_L2_size_bytes(struct gk20a *g)
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{
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u32 reg_val;
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u32 slice_size;
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u32 slices_per_l2;
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u64 ret;
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nvgpu_log_fn(g, " ");
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reg_val = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
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slice_size = ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(reg_val);
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slices_per_l2 = ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(reg_val);
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ret = nvgpu_safe_mult_u64(g->ltc->ltc_count,
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nvgpu_safe_mult_u64(
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nvgpu_safe_mult_u64(U64(slice_size), 1024ULL),
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U64(slices_per_l2)));
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nvgpu_log(g, gpu_dbg_info, "L2 size: %llu\n", ret);
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nvgpu_log_fn(g, "done");
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return ret;
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}
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void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
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{
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u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
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u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
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if (enabled) {
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/* bypass disabled (normal caching ops) */
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reg &= ~reg_f;
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} else {
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/* bypass enabled (no caching) */
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reg |= reg_f;
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}
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nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
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}
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