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c36752fe3d
The simulator ring buffer DMA interface supports buffers of the following sizes: 4, 8, 12 and 16K. At present, it is configured to 4K and it happens to match with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once 4K is reached. However, this is not always true; for instance, take 64K pages. Hence, replace PAGE_SIZE with SIM_BFR_SIZE. Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace latter with former. Bug 200658101 Jira NVGPU-6018 Change-Id: I83cc62b87291734015c51f3e5a98173549e065de Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
2.1 KiB
C
59 lines
2.1 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/mm.h>
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#include "mm_gk20a.h"
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void gk20a_mm_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
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u32 big_page_size)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
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nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
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nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
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g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
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g->ops.ramin.set_adr_limit(g, inst_block, vm->va_limit - 1U);
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if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
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g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
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}
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}
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#ifdef CONFIG_NVGPU_USERD
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u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u64 gpu_va = f->userd_gpu_va + offset;
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return nvgpu_gmmu_map_fixed(g->mm.bar1.vm, mem, gpu_va,
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NVGPU_CPU_PAGE_SIZE, 0,
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gk20a_mem_flag_none, false,
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mem->aperture);
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}
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#endif
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