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87984ea344
Enable nvriscv debug buffer feature in NVGPU. Debug buffer is a feature to print the debug log from ucode onto console in real time. Debug buffer feature uses the DMEM, queue and SWGEN1 interrupt to share ucode debug data with NVGPU. Ucode writes debug message to DMEM and updates offset in queue to trigger interrupt to NVGPU. NVGPU copies the debug message from DMEM to local buffer to process and print onto console. Debug buffer feature is added under falcon unit and required engine can utilize the feature by providing required param through public functions. Currently GA10B NVRISCV NS/LS PMU ucode has support for this feature and enabled support on NVGPU side by adding required changes, with this feature enabled, it is now possible to see prints in real time. JIRA NVGPU-6959 Change-Id: I9d46020470285b490b6bc876204f62698055b1ec Signed-off-by: mkumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548951 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_GA10B_H
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#define NVGPU_PMU_GA10B_H
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#include <nvgpu/types.h>
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#define DMA_OFFSET_START 0U
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#define DMEM_DATA_0 0x0U
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#define DMEM_DATA_1 0x1U
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#define PMU_IDLE_THRESHOLD_V 0x7FFFFFFF
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#define IDLE_COUNTER_0 0
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#define IDLE_COUNTER_1 1
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#define IDLE_COUNTER_2 2
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#define IDLE_COUNTER_3 3
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#define IDLE_COUNTER_4 4
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#define IDLE_COUNTER_6 6
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#define right_shift_8bits(v) (v >> 8U)
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#define left_shift_8bits(v) (v << 8U)
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struct gk20a;
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struct nvgpu_pmu;
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bool ga10b_is_pmu_supported(struct gk20a *g);
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u32 ga10b_pmu_falcon2_base_addr(void);
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int ga10b_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 args_offset);
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u32 ga10b_pmu_get_inst_block_config(struct gk20a *g);
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void ga10b_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
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void ga10b_pmu_init_perfmon_counter(struct gk20a *g);
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u32 ga10b_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
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void ga10b_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
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u32 ga10b_pmu_get_irqmask(struct gk20a *g);
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bool ga10b_pmu_is_debug_mode_en(struct gk20a *g);
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void ga10b_pmu_handle_swgen1_irq(struct gk20a *g, u32 intr);
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#endif /* NVGPU_PMU_GA10B_H */
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