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1ff79b1d2c
quad type reg_ops were only needed on Kepler, and not for any other chip beginning Maxweel. HAL g->ops.gr.access_smpc_reg() was incorrectly set for Volta and Turing whereas it was only applicable to Kepler. Delete it. There is no register in the quad type whitelist since the type itself is not supported anymore. Remove the empty whitelists for all chips and also delete below HALs: g->ops.regops.get_qctl_whitelist() g->ops.regops.get_qctl_whitelist_count() hal/regops/regops_gv100.* files are not used anymore. Delete the files instead of just deleting quad HALs in these files. Bug 200628391 Change-Id: I4dcc04bef5c24eb4d63d913f492a8c00543163a2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366035 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
38 lines
1.8 KiB
C
38 lines
1.8 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_TU104_H
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#define NVGPU_REGOPS_TU104_H
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#ifdef CONFIG_NVGPU_DEBUGGER
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const struct regop_offset_range *tu104_get_global_whitelist_ranges(void);
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u64 tu104_get_global_whitelist_ranges_count(void);
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const struct regop_offset_range *tu104_get_context_whitelist_ranges(void);
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u64 tu104_get_context_whitelist_ranges_count(void);
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const u32 *tu104_get_runcontrol_whitelist(void);
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u64 tu104_get_runcontrol_whitelist_count(void);
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const struct regop_offset_range *tu104_get_runcontrol_whitelist_ranges(void);
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u64 tu104_get_runcontrol_whitelist_ranges_count(void);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif /* NVGPU_REGOPS_TU104_H */
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