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d255c64f50
To keep pdiv_duration at 15usec between steps at 102MHz utilsclk, update stepping duration value from 0xBF4 to 0x5FA for ga10x. Bug 200757274 Change-Id: I333a5b0b35307402a734a7eafc4ab13d20316cd1 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2584539 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
93 lines
3.1 KiB
C
93 lines
3.1 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/device.h>
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#include <nvgpu/power_features/cg.h>
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#include "therm_ga10b.h"
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#include <nvgpu/hw/ga10b/hw_therm_ga10b.h>
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u32 ga10b_therm_max_fpdiv_factor(void)
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{
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/* minimum duration between steps 15usec * UTILSCLK@102 MHz */
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return 0x5FA;
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}
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u32 ga10b_therm_grad_stepping_pdiv_duration(void)
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{
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return therm_grad_stepping_table_slowdown_factor0_fpdiv_by31_f();
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}
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int ga10b_elcg_init_idle_filters(struct gk20a *g)
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{
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u32 gate_ctrl, idle_filter;
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u32 i;
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const struct nvgpu_device *dev;
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struct nvgpu_fifo *f = &g->fifo;
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if (nvgpu_platform_is_simulation(g)) {
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return 0;
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}
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nvgpu_log_info(g, "init clock/power gate reg");
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for (i = 0U; i < f->num_engines; i++) {
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dev = f->active_engines[i];
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gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(dev->engine_id));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_exp_m(),
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therm_gate_ctrl_eng_idle_filt_exp__prod_f());
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_mant_m(),
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therm_gate_ctrl_eng_idle_filt_mant__prod_f());
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_before_m(),
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therm_gate_ctrl_eng_delay_before__prod_f());
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_after_m(),
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therm_gate_ctrl_eng_delay_after__prod_f());
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nvgpu_writel(g, therm_gate_ctrl_r(dev->engine_id), gate_ctrl);
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}
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idle_filter = nvgpu_readl(g, therm_fecs_idle_filter_r());
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idle_filter = set_field(idle_filter,
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therm_fecs_idle_filter_value_m(),
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therm_fecs_idle_filter_value__prod_f());
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nvgpu_writel(g, therm_fecs_idle_filter_r(), idle_filter);
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idle_filter = nvgpu_readl(g, therm_hubmmu_idle_filter_r());
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idle_filter = set_field(idle_filter,
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therm_hubmmu_idle_filter_value_m(),
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therm_hubmmu_idle_filter_value__prod_f());
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nvgpu_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
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return 0;
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}
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