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84a24c9593
- Remove non-safe TPC powergate feature from the safety build by introducing a new flag: CONFIG_NVGPU_TPC_POWERGATE - Move nvgpu_init_power_gate_gr() under same compile time flag. and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c - Also, remove the negative test scenario and usage of tpc_powergate from unit tests JIRA NVGPU-4149 Change-Id: If489482401e94de499e472b16b1bc091b00992e6 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2242323 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* GV11B TPC
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*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include "tpc_gv11b.h"
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int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status)
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{
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int err = 0;
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if (fuse_status == 0x0) {
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g->can_tpc_powergate = true;
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} else {
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/* if hardware has already floorswept any TPC
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* (fuse_status != 0x0) and if TPC PG mask
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* sent from userspace is 0x0 GPU will be powered on
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* with the default fuse_status setting. It cannot
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* un-floorsweep any TPC
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* thus, set g->tpc_pg_mask to fuse_status value
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*/
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if (g->tpc_pg_mask == 0x0) {
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g->can_tpc_powergate = true;
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g->tpc_pg_mask = fuse_status;
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} else if (fuse_status == g->tpc_pg_mask) {
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g->can_tpc_powergate = true;
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} else if ((fuse_status & g->tpc_pg_mask) ==
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fuse_status) {
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g->can_tpc_powergate = true;
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} else {
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/* If userspace sends a TPC PG mask such that
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* it tries to un-floorsweep any TPC which is
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* already powergated from hardware, then
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* such mask is invalid.
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* In this case set tpc pg mask to 0x0
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* Return -EINVAL here and halt GPU poweron.
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*/
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nvgpu_err(g, "Invalid TPC_PG mask: 0x%x",
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g->tpc_pg_mask);
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g->can_tpc_powergate = false;
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g->tpc_pg_mask = 0x0;
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err = -EINVAL;
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}
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}
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return err;
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}
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void gv11b_gr_pg_tpc(struct gk20a *g)
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{
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u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
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if (tpc_pg_status == g->tpc_pg_mask) {
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return;
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}
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g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask);
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do {
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tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
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} while (tpc_pg_status != g->tpc_pg_mask);
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return;
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}
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