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767e505792
The devinit executes in parallel with PCIE link training to reduce exit latency. Therefore, all PCIE settings that normally occur during devinit after the PCIE link is up are deferred until nvgpu has resumed control. Bug 2661545 Change-Id: Ifdd4f645b2e1791d93567cc34d6ab0691a25d101 Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2210625 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/xve.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include "xve_tu104.h"
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#include "xve_gp106.h"
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#include <nvgpu/hw/tu104/hw_xve_tu104.h>
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#include <nvgpu/hw/tu104/hw_xp_tu104.h>
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#define DL_TIMER_LIMIT 0x58EU
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void tu104_devinit_deferred_settings(struct gk20a *g)
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{
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u32 data;
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g->ops.xve.xve_writel(g, xve_pcie_capability_r(),
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xve_pcie_capability_gen2_capable_enable_f() |
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xve_pcie_capability_gen3_capable_enable_f());
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nvgpu_writel(g, xp_dl_mgr_timing_r(0), DL_TIMER_LIMIT);
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data = xve_high_latency_snoop_latency_value_init_f() |
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xve_high_latency_snoop_latency_scale_init_f() |
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xve_high_latency_no_snoop_latency_value_init_f() |
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xve_high_latency_no_snoop_latency_scale_init_f();
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g->ops.xve.xve_writel(g, xve_high_latency_r(), data);
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g->ops.xve.xve_writel(g, xve_ltr_msg_ctrl_r(),
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xve_ltr_msg_ctrl_trigger_not_pending_f());
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}
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