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4edf952e3e
Fix rule 5.1 misra violations in common.gr by renaming below functions : nvgpu_gr_config_get_gpc_tpc_mask_base -> nvgpu_gr_config_get_base_mask_gpc_tpc nvgpu_gr_config_get_gpc_tpc_count_base -> nvgpu_gr_config_get_base_count_gpc_tpc gm20b_ctxsw_prog_set_priv_access_map_config_mode -> gm20b_ctxsw_prog_set_config_mode_priv_access_map gm20b_ctxsw_prog_set_priv_access_map_addr -> gm20b_ctxsw_prog_set_addr_priv_access_map gm20b_gr_falcon_read_fecs_ctxsw_mailbox -> gm20b_gr_falcon_read_mailbox_fecs_ctxsw gm20b_gr_falcon_read_fecs_ctxsw_status0 -> gm20b_gr_falcon_read_status0_fecs_ctxsw gm20b_gr_falcon_read_fecs_ctxsw_status1 -> gm20b_gr_falcon_read_status1_fecs_ctxsw gv11b_gr_intr_get_sm_hww_warp_esr_pc -> gv11b_gr_intr_get_warp_esr_pc_sm_hww gv11b_gr_intr_get_sm_hww_warp_esr -> gv11b_gr_intr_get_warp_esr_sm_hww Jira NVGPU-6779 Change-Id: Icbe23a7b022373785968fc417ee247e2d80cfcc6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554521 (cherry picked from commit 1432650774506f2a7e45f70b084f498736d0d0c5) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555330 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
303 lines
12 KiB
C
303 lines
12 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_GR_INTR_H
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#define UNIT_NVGPU_GR_INTR_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct unit_module;
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/** @addtogroup SWUTS-gr-intr
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* @{
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*
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* Software Unit Test Specification for common.gr.intr
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*/
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/**
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* Test specification for: test_gr_intr_without_channel.
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*
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* Description: This test helps to verify the stall interrupts for some
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* common.gr subunits without any channel allocation.
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* Also helps to verify the nonstall interrupts.
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*
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* Test Type: Feature, Error guessing
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*
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* Targets: gops_gr_intr.stall_isr, nvgpu_gr_intr_stall_isr,
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* gops_gr_intr.nonstall_isr, gm20b_gr_intr_nonstall_isr,
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* nvgpu_gr_intr_init_support,
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* nvgpu_gr_intr_handle_fecs_error,
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* gops_gr_falcon.dump_stats,
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* gm20b_gr_falcon_fecs_dump_stats,
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* gm20b_gr_falcon_read_status1_fecs_ctxsw,
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* gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
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* gm20b_gr_falcon_fecs_host_clear_intr,
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* nvgpu_gr_intr_remove_support
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Set exception for FE, MEMFMT, PD, SCC, DS, SSYNC, MME, SKED
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* in gr interrupt register.
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* - Set Error injection for allocation, fecs and exception interrupts
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* without properly setting the valid needed sub interrupts.
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* - Call g->ops.gr.intr.stall_isr.
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* - Call g->ops.gr.intr.nonstall_isr without nonstall pending interrupt set.
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* - Set nonstall trap pending interrupt bit.
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* - Call g->ops.gr.intr.nonstall_isr.
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* - g->ops.gr.intr.handle_ssync_hww to NULL.
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* - Call g->ops.gr.intr.nonstall_isr.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_intr_without_channel(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_intr_setup_channel.
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*
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* Description: This test helps to verify the stall interrupts for some
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* common.gr subunits with channel and tsg allocation.
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* Helps to figure out the current context on interrupt
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* pending with subunit error.
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*
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* Test Type: Feature, Error guessing
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*
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* Targets: nvgpu_gr_intr_stall_isr,
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* gops_gr_intr.handle_notify_pending,
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* nvgpu_gr_intr_handle_notify_pending,
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* gops_gr_intr.handle_semaphore_pending,
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* nvgpu_gr_intr_handle_semaphore_pending,
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* gops_gr_intr.handle_class_error,
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* gm20b_gr_intr_handle_class_error,
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* gm20b_gr_falcon_get_current_ctx,
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* gm20b_gr_falcon_get_ctx_ptr,
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* nvgpu_gr_intr_get_channel_from_ctx,
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* nvgpu_gr_get_intr_ptr,
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* nvgpu_gr_intr_remove_support
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Setup channel and tsg and bing tsg & channel.
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* - nvgpu_channel_setup_sw & nvgpu_tsg_setup_sw.
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* - nvgpu_tsg_open_new & nvgpu_tsg_channel_open_new.
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* - nvgpu_tsg_bind_channel.
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* - Negative test - without setting the current context.
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* - Call g->ops.gr.intr.stall_isr.
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* - Set Notify and Semaphore wait_queue uninitialized.
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* - Call g->ops.gr.intr.stall_isr.
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* - Positive test.
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* - Set tsgid as the current context.
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* - Set local cache.
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* - Call g->ops.gr.intr.stall_isr.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_intr_setup_channel(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_intr_sw_exceptions.
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*
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* Description: Helps to verify pending interrupts for illegal method.
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* Helps to verify exceptions for SET_SHADER_EXCEPTIONS,
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* SET_SKEDCHECK and SET_SHADER_CUT_COLLECTOR.
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*
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* Test Type: Feature, Error guessing
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*
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* Targets: gops_gr_intr.stall_isr, nvgpu_gr_intr_stall_isr,
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* gops_gr_intr.flush_channel_tlb, nvgpu_gr_intr_flush_channel_tlb,
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* gops_gr_intr.handle_sw_method,
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* gv11b_gr_intr_handle_sw_method,
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* gv11b_gr_intr_set_skedcheck,
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* gv11b_gr_intr_set_shader_cut_collector,
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* gops_gr_intr.trapped_method_info,
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* gm20b_gr_intr_get_trapped_method_info,
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* nvgpu_gr_intr_set_error_notifier,
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* nvgpu_gr_intr_report_exception
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Setup illegal method pending interrupt bit.
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* - Set the illegal method trapped addresses and datas.
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* - Set invalid class and data.
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* - Call g->ops.gr.intr.stall_isr.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_intr_sw_exceptions(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_intr_fecs_exceptions.
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*
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* Description: Helps to verify pending interrupts for fecs exceptions.
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* Helps to verify exceptions for ctxsw_interrupts,
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* fault_during_ctxsw, unimp_firmware_method,
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* unimpl_illegal_method, watchdog, ecc_corrected and
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* ecc_uncorrected interrupts.
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*
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* Test Type: Feature, Error guessing
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*
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* Targets: gops_gr_intr.stall_isr, nvgpu_gr_intr_stall_isr,
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* gops_gr_intr.handle_fecs_error, gv11b_gr_intr_handle_fecs_error,
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* gp10b_gr_intr_handle_fecs_error,
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* gops_gr_intr.get_ctxsw_checksum_mismatch_mailbox_val,
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* gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
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* gops_gr_falcon.read_fecs_ctxsw_mailbox,
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* gm20b_gr_falcon_read_mailbox_fecs_ctxsw,
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* gops_gr_falcon.dump_stats,
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* gm20b_gr_falcon_fecs_dump_stats,
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* gm20b_gr_falcon_read_status1_fecs_ctxsw,
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* gm20b_gr_falcon_read_status0_fecs_ctxsw,
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* gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
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* gm20b_gr_falcon_fecs_host_clear_intr,
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* gm20b_gr_falcon_fecs_host_intr_status,
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* gv11b_gr_falcon_handle_fecs_ecc_error,
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* nvgpu_gr_intr_set_error_notifier,
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* nvgpu_gr_intr_report_exception
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Set fecs exception interrupt bits.
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* - Set fecs pending interrupt bit.
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* - Set various ecc error register combinations.
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* - Call g->ops.gr.intr.stall_isr.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_intr_fecs_exceptions(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_gr_intr_gpc_exceptions.
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*
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* Description: Helps to verify pending interrupts for gpc_exceptions.
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*
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* Test Type: Feature, Error guessing
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*
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* Targets: nvgpu_gr_intr_handle_gpc_exception,
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* gops_gr_intr.read_gpc_exception,
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* gm20b_gr_intr_read_gpc_exception,
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* gops_gr_intr.read_exception1, gm20b_gr_intr_read_exception1,
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* gops_gr_intr.handle_exceptions,
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* gm20b_gr_intr_handle_exceptions,
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* gops_gr_intr.read_gpc_tpc_exception,
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* gm20b_gr_intr_read_gpc_tpc_exception,
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* gops_gr_intr.handle_gpc_gpccs_exception,
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* gv11b_gr_intr_handle_gpc_gpccs_exception,
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* gops_gr_intr.handle_gpc_gpcmmu_exception,
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* gv11b_gr_intr_handle_gpc_gpcmmu_exception,
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* gops_gr_intr.handle_gcc_exception,
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* gv11b_gr_intr_handle_gcc_exception,
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* gops_gr_intr.handle_sm_exception,
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* nvgpu_gr_intr_handle_sm_exception,
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* gops_gr_intr.get_tpc_exception, gm20b_gr_intr_get_tpc_exception,
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* gops_gr_intr.handle_gpc_setup_exception,
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* gv11b_gr_intr_handle_gpc_setup_exception,
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* gops_gr_intr.handle_gpc_prop_exception,
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* gv11b_gr_intr_handle_gpc_prop_exception,
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* gops_gr_intr.handle_gpc_pes_exception,
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* gv11b_gr_intr_handle_gpc_pes_exception,
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* gops_gr_intr.handle_gpc_zcull_exception,
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* gv11b_gr_intr_handle_gpc_zcull_exception,
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* gops_gr_intr.handle_tpc_sm_ecc_exception,
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* gv11b_gr_intr_handle_tpc_sm_ecc_exception,
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* gops_gr_intr.handle_tpc_mpc_exception,
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* gv11b_gr_intr_handle_tpc_mpc_exception,
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* gops_gr_intr.handle_tpc_pe_exception,
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* gv11b_gr_intr_handle_tpc_pe_exception,
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* gops_gr_intr.set_hww_esr_report_mask,
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* gv11b_gr_intr_set_hww_esr_report_mask,
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* gops_gr_intr.get_esr_sm_sel, gv11b_gr_intr_get_esr_sm_sel,
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* gops_gr_intr.clear_sm_hww, gv11b_gr_intr_clear_sm_hww,
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* gops_gr_intr.handle_ssync_hww, gv11b_gr_intr_handle_ssync_hww,
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* gops_gr_intr.record_sm_error_state,
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* gv11b_gr_intr_record_sm_error_state,
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* gops_gr_intr.get_sm_hww_warp_esr,
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* gv11b_gr_intr_get_warp_esr_sm_hww,
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* gops_gr_intr.get_sm_hww_warp_esr_pc,
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* gv11b_gr_intr_get_warp_esr_sm_hww_pc,
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* gops_gr_intr.get_sm_hww_global_esr,
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* gv11b_gr_intr_get_sm_hww_global_esr,
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* gops_gr_intr.get_sm_no_lock_down_hww_global_esr_mask,
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* gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
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* nvgpu_gr_intr_set_error_notifier,
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* nvgpu_gr_intr_stall_isr,
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* gops_gr_intr.read_pending_interrupts,
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* gm20b_gr_intr_read_pending_interrupts,
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* gops_gr_intr.clear_pending_interrupts,
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* gm20b_gr_intr_clear_pending_interrupts,
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* nvgpu_gr_gpc_offset,
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* nvgpu_gr_tpc_offset,
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* nvgpu_gr_sm_offset
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*
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* Input: #test_gr_init_setup_ready must have been executed successfully.
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*
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* Steps:
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* - Making use of functions for following tests
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* - g->ops.gr.intr.handle_tpc_sm_ecc_exception.
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* - g->ops.gr.intr.handle_gpc_gpcmmu_exception.
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* - g->ops.gr.intr.handle_gpc_gpccs_exception.
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* - g->ops.gr.intr.handle_gcc_exception.
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* - g->ops.gr.intr.stall_isr.
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* - Negative tests.
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* - Verify gpc exceptions with setting any gpc exception bits but
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* enable the pending gpc exception interrupt bit.
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* - Verify gpc exceptions by setting gpc exception bits and
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* enable the pending gpc exception interrupt bit.Without setting
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* ecc status registers.
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* - Verify tpc_exception interrupt with NULL gpc and tpc hals
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* and enabling gpc_tpc_exceptions.
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* - Verify gpc exceptions by setting gpc exception bits,
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* ecc status registers and the pending gpc exception interrupt bit.
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* Without setting SM ESR registers.
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* - Verify gpc and tpc_exceptions with various ecc registers value
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* combinations for overflow and corrected and uncorrected errors.
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* - Positive test.
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* - Verify gpc exceptions by setting gpc exception bits,
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* tpc exception bits, ecc status registers, setting SM ESR registers
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* and the pending gpc exception interrupt bit.
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*
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* Output: Returns PASS if the steps above were executed successfully. FAIL
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* otherwise.
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*/
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int test_gr_intr_gpc_exceptions(struct unit_module *m,
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struct gk20a *g, void *args);
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#endif /* UNIT_NVGPU_GR_INTR_H */
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/**
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* @}
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*/
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