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df4e88a21d
In t19x, gv11b semaphore read and write operations are translated to host1x syncpoint read and write operations using semaphore syncpoint shim aperture. Implement relevant vgpu hal functions for this in fifo hal. Jira EVLR-1571 Change-Id: I6296cc6e592ea991e1c01bc9662d02fb063ff3c7 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516367 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <gk20a/gk20a.h>
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#include "vgpu/vgpu.h"
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#include "gv11b/fifo_gv11b.h"
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#include <nvgpu/nvhost_t19x.h>
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#include <linux/tegra_vgpu.h>
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
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u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
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{
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int err;
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struct gk20a *g = c->g;
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struct vm_gk20a *vm = c->vm;
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt;
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/*
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* Add ro map for complete sync point shim range in vm.
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* All channels sharing same vm will share same ro mapping.
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* Create rw map for current channel sync point.
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*/
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if (!vm->syncpt_ro_map_gpu_va) {
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vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm,
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g->syncpt_unit_size,
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gmmu_page_size_kernel);
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if (!vm->syncpt_ro_map_gpu_va) {
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nvgpu_err(g, "allocating read-only va space failed");
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return -ENOMEM;
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}
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msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
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msg.handle = vgpu_get_handle(g);
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p->as_handle = c->vm->handle;
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p->gpu_va = vm->syncpt_ro_map_gpu_va;
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p->len = g->syncpt_unit_size;
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p->offset = 0;
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p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g,
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"mapping read-only va space failed err %d",
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err);
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__nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va,
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gmmu_page_size_kernel);
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vm->syncpt_ro_map_gpu_va = 0;
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return err;
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}
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}
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syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size,
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gmmu_page_size_kernel);
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if (!syncpt_buf->gpu_va) {
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nvgpu_err(g, "allocating syncpt va space failed");
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return -ENOMEM;
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}
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msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT;
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msg.handle = vgpu_get_handle(g);
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p->as_handle = c->vm->handle;
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p->gpu_va = syncpt_buf->gpu_va;
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p->len = g->syncpt_size;
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p->offset =
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nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
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p->prot = TEGRA_VGPU_MAP_PROT_NONE;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(g, "mapping syncpt va space failed err %d", err);
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__nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va,
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gmmu_page_size_kernel);
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return err;
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}
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return 0;
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}
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#endif /* CONFIG_TEGRA_GK20A_NVHOST */
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int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
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{
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struct fifo_gk20a *f = &g->fifo;
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int err;
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err = vgpu_get_attribute(vgpu_get_handle(g),
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TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT,
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&f->t19x.max_subctx_count);
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if (err) {
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nvgpu_err(g, "get max_subctx_count failed %d", err);
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return err;
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}
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return 0;
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}
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