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d61643c020
Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
80 lines
2.7 KiB
C
80 lines
2.7 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <gk20a/gk20a.h>
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#include <vgpu/vgpu.h>
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#include <linux/tegra_vgpu.h>
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int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
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{
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struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_alloc_ctx_header_params *p =
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&msg.params.t19x.alloc_ctx_header;
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struct gr_gk20a *gr = &c->g->gr;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
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msg.handle = vgpu_get_handle(c->g);
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p->ch_handle = c->virt_ctx;
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p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
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gr->ctx_vars.golden_image_size,
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gmmu_page_size_kernel);
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if (!p->ctx_header_va) {
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nvgpu_err(c->g, "alloc va failed for ctx_header");
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return -ENOMEM;
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}
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (unlikely(err)) {
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nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
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__nvgpu_vm_free_va(c->vm, p->ctx_header_va,
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gmmu_page_size_kernel);
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return err;
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}
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ctx->mem.gpu_va = p->ctx_header_va;
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return err;
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}
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void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
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{
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struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_free_ctx_header_params *p =
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&msg.params.t19x.free_ctx_header;
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int err;
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if (ctx->mem.gpu_va) {
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msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
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msg.handle = vgpu_get_handle(c->g);
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p->ch_handle = c->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (unlikely(err))
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nvgpu_err(c->g, "free ctx_header failed err %d", err);
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__nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
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gmmu_page_size_kernel);
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ctx->mem.gpu_va = 0;
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}
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}
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