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git://nv-tegra.nvidia.com/linux-nvgpu.git
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04d9de8478
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I248295107c5959a98ff00917e0474bcd03708156 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457356 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/*
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* Linux clock support
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include "gk20a/gk20a.h"
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static unsigned long nvgpu_linux_clk_get_rate(struct gk20a *g, u32 api_domain)
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{
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struct gk20a_platform *platform = gk20a_get_platform(g->dev);
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unsigned long ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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if (g->clk.tegra_clk)
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ret = clk_get_rate(g->clk.tegra_clk);
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else
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ret = clk_get_rate(platform->clk[0]);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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ret = clk_get_rate(platform->clk[1]);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = 0;
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break;
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}
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return ret;
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}
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static int nvgpu_linux_clk_set_rate(struct gk20a *g,
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u32 api_domain, unsigned long rate)
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{
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struct gk20a_platform *platform = gk20a_get_platform(g->dev);
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int ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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if (g->clk.tegra_clk)
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ret = clk_set_rate(g->clk.tegra_clk, rate);
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else
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ret = clk_set_rate(platform->clk[0], rate);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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ret = clk_set_rate(platform->clk[1], rate);
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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void nvgpu_linux_init_clk_support(struct gk20a *g)
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{
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g->ops.clk.get_rate = nvgpu_linux_clk_get_rate;
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g->ops.clk.set_rate = nvgpu_linux_clk_set_rate;
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}
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