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76792585b5
On ga10b+ platforms, more VM space is needed to map various buffers
to bar2 vm. Engine method buffer is mapped for each pbdma and for
maximum supported TSGs this requires more than 32MB of space.
Also we need to consider fault buffer space and vab buffer
space requirement.
Bug 3958581
Change-Id: I9ee87119f762352ee12859b71c08a5f75b3554e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872811
(cherry picked from commit 53dc53a8b4)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2881179
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
73 lines
2.6 KiB
C
73 lines
2.6 KiB
C
/*
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* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/hw/ga10b/hw_gmmu_ga10b.h>
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#include "mm_ga10b.h"
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u32 ga10b_mm_bar2_vm_size(struct gk20a *g)
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{
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u32 num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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u32 buffer_size;
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u32 fb_size;
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/* Calculate engine method buffer size */
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buffer_size = nvgpu_safe_add_u32(nvgpu_safe_mult_u32((9U + 1U + 3U),
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g->ops.ce.get_num_pce(g)), 2U);
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buffer_size = nvgpu_safe_mult_u32((27U * 5U), buffer_size);
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buffer_size = PAGE_ALIGN(buffer_size);
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nvgpu_log_info(g, "method buffer size in bytes %u", buffer_size);
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buffer_size = nvgpu_safe_mult_u32(num_pbdma, buffer_size);
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buffer_size = nvgpu_safe_mult_u32(buffer_size, g->ops.channel.count(g));
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nvgpu_log_info(g, "method buffer size in bytes for max TSGs %u",
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buffer_size);
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/*
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* Calculate fault buffers size.
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* Max entries take care of 1 entry used for full detection.
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*/
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fb_size = nvgpu_safe_add_u32(g->ops.channel.count(g), 1U);
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fb_size = nvgpu_safe_mult_u32(fb_size, gmmu_fault_buf_size_v());
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/* Consider replayable and non replayable faults */
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fb_size = nvgpu_safe_mult_u32(fb_size, 2U);
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nvgpu_log_info(g, "fault buffers size in bytes %u", fb_size);
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buffer_size = nvgpu_safe_add_u32(buffer_size, fb_size);
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/* Add PAGE_SIZE for vab buffer size */
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buffer_size = nvgpu_safe_add_u32(buffer_size, PAGE_SIZE);
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buffer_size = PAGE_ALIGN(buffer_size);
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nvgpu_log_info(g, "bar2 vm size in bytes %u", buffer_size);
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return buffer_size;
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}
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