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dddeee54b6
Use hardware headers instead of hardcoded register numbers in priv ring. This required updating the priv ring headers to add all the registers and fields needed. Incidentally this also gets rid of a lot of GPC priv ring registers as they're not used in our code. Also delete duplicate prints for the same information. We were dumping GPC error also in gk20a_pbus_isr(), and we dumped master information twice. Dump status of each GPC separately instead of supporting only GPC0. Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295481 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
127 lines
4.1 KiB
C
127 lines
4.1 KiB
C
/*
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* GK20A priv ring
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h> /* for mdelay */
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#include "gk20a.h"
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#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
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void gk20a_enable_priv_ring(struct gk20a *g)
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{
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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if (platform->is_fmodel)
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return;
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if (g->ops.clock_gating.slcg_priring_load_gating_prod)
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g->ops.clock_gating.slcg_priring_load_gating_prod(g,
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g->slcg_enabled);
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gk20a_writel(g,pri_ringmaster_command_r(),
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0x4);
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gk20a_writel(g, pri_ringstation_sys_decode_config_r(),
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0x2);
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gk20a_readl(g, pri_ringstation_sys_decode_config_r());
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}
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static void gk20a_reset_priv_ring(struct gk20a *g)
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{
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u32 val;
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gk20a_reset(g, mc_enable_priv_ring_enabled_f());
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val = gk20a_readl(g, pri_ringstation_sys_decode_config_r());
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val = set_field(val,
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pri_ringstation_sys_decode_config_ring_m(),
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pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f());
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gk20a_writel(g, pri_ringstation_sys_decode_config_r(), val);
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gk20a_writel(g, pri_ringmaster_global_ctl_r(),
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pri_ringmaster_global_ctl_ring_reset_asserted_f());
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udelay(20);
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gk20a_writel(g, pri_ringmaster_global_ctl_r(),
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pri_ringmaster_global_ctl_ring_reset_deasserted_f());
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gk20a_enable_priv_ring(g);
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}
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void gk20a_priv_ring_isr(struct gk20a *g)
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{
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u32 status0, status1;
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u32 cmd;
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s32 retry = 100;
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u32 gpc;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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struct gk20a_platform *platform = dev_get_drvdata(g->dev);
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if (platform->is_fmodel)
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return;
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status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
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status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
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gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
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"status1: 0x%08x", status0, status1);
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if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 ||
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pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0 ||
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pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
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gk20a_reset_priv_ring(g);
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}
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if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
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gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
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gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
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gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
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}
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for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
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if (status1 & BIT(gpc)) {
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gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
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gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
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}
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}
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cmd = gk20a_readl(g, pri_ringmaster_command_r());
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cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
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pri_ringmaster_command_cmd_ack_interrupt_f());
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gk20a_writel(g, pri_ringmaster_command_r(), cmd);
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do {
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cmd = pri_ringmaster_command_cmd_v(
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gk20a_readl(g, pri_ringmaster_command_r()));
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usleep_range(20, 40);
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} while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry);
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if (retry <= 0)
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gk20a_warn(dev_from_gk20a(g),
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"priv ringmaster cmd ack too many retries");
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}
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