mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
8a411096c9
For PCIE gpu device, it uses PCIE controller dt node to store nvgpu/vgpu dt properties, since PCIE endpoint device does not have any corresponding dt node. So we pass dt_node directly to tegra_gr_comm, together with EP device since tegra_gr_comm relies on dev_err. Jira GVSCI-15779 Change-Id: I73c5210e2d8b6a728c74823c1e62fed765776365 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884176 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Austin Tajiri <atajiri@nvidia.com> Reviewed-by: Santosh BS <santoshb@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
/*
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* Copyright (c) 2018-2023, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/types.h>
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#include <linux/tegra_gr_comm.h>
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#include "os/linux/os_linux.h"
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#include "os/linux/module.h"
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int vgpu_ivc_init(struct gk20a *g, u32 elems,
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const size_t *queue_sizes, u32 queue_start, u32 num_queues)
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{
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struct device *dev = dev_from_gk20a(g);
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return tegra_gr_comm_init(dev, nvgpu_get_node(g), elems,
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queue_sizes, queue_start,
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num_queues);
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}
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void vgpu_ivc_deinit(u32 queue_start, u32 num_queues)
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{
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tegra_gr_comm_deinit(queue_start, num_queues);
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}
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void vgpu_ivc_release(void *handle)
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{
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tegra_gr_comm_release(handle);
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}
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u32 vgpu_ivc_get_server_vmid(void)
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{
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return tegra_gr_comm_get_server_vmid();
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}
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int vgpu_ivc_recv(u32 index, void **handle, void **data,
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size_t *size, u32 *sender)
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{
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return tegra_gr_comm_recv(index, handle, data, size, sender);
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}
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int vgpu_ivc_send(u32 peer, u32 index, void *data, size_t size)
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{
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return tegra_gr_comm_send(peer, index, data, size);
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}
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int vgpu_ivc_sendrecv(u32 peer, u32 index, void **handle,
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void **data, size_t *size)
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{
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return tegra_gr_comm_sendrecv(peer, index, handle, data, size);
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}
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u32 vgpu_ivc_get_peer_self(void)
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{
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return TEGRA_GR_COMM_ID_SELF;
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}
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void *vgpu_ivc_oob_get_ptr(u32 peer, u32 index, void **ptr,
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size_t *size)
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{
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return tegra_gr_comm_oob_get_ptr(peer, index, ptr, size);
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}
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void vgpu_ivc_oob_put_ptr(void *handle)
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{
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tegra_gr_comm_oob_put_ptr(handle);
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}
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