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git://nv-tegra.nvidia.com/linux-nvgpu.git
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94bc3a8135
Update nvgpu_gr_zbc as:
struct nvgpu_gr_zbc {
struct nvgpu_mutex zbc_lock; /* Lock to access zbc table */
struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
u32 min_color_index; /* Minimum valid color table index */
u32 min_depth_index; /* Minimum valid depth table index */
u32 min_stencil_index; /* Minimum valid stencil table index */
u32 max_color_index; /* Maximum valid color table index */
u32 max_depth_index; /* Maximum valid depth table index */
u32 max_stencil_index; /* Maximum valid stencil table index */
u32 max_used_color_index; /* Max used color table index */
u32 max_used_depth_index; /* Max used depth table index */
u32 max_used_stencil_index; /* Max used stencil table index */
};
Add global struct nvgpu_gr_zbc_table_indices
struct nvgpu_gr_zbc_table_indices {
u32 min_color_index;
u32 min_depth_index;
u32 min_stencil_index;
u32 max_color_index;
u32 max_depth_index;
u32 max_stencil_index;
};
Currently, hw zbc table registers are written during both
gr_init_setup_sw() and gr_init_setup_hw().
- Modify nvgpu_gr_zbc_load_default_table() to
nvgpu_gr_zbc_load_default_sw_table() to only update sw copy of zbc table
during gr_init_setup_sw().
- Modify nvgpu_gr_zbc_load_table() to write zbc values stored in sw zbc
table to hw registers.
Re-structure zbc function as per zbc type i.e. color, depth and stencil.
Add gr.zbc.init_table_indices() hal to initialize zbc indices. Valid ZBC
table indices start from 1. HW indices start from 0 for color, depth and
stencil tables. Note that the corresponding format registers follow ZBC
index range starting at 1.
- void (*init_table_indices)(struct gk20a *g,
struct nvgpu_gr_zbc_table_indices *zbc_indices);
- Add corresponding functions for legacy chips
- Add zbc color, depth and stencil table size hw defines
- Remove ltc.zbc_table_size() hal
- Update ltc.set_zbc_s_entry(), ltc.set_zbc_color_entry and
ltc.set_zbc_depth_entry() accordingly.
Bug 3122410
Bug 3122649
Change-Id: Ib799991ad35c6613534c0a6eb07f3bf24e600dc5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417620
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
108 lines
3.6 KiB
C
108 lines
3.6 KiB
C
/*
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* GV11B LTC
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/gr/zbc.h>
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#include "ltc_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
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#include <nvgpu/utils.h>
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#ifdef CONFIG_NVGPU_GRAPHICS
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/*
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* Sets the ZBC stencil for the passed index.
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*/
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void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
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u32 stencil_depth,
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u32 index)
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{
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nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
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ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
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nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
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stencil_depth);
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}
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#endif /* CONFIG_NVGPU_GRAPHICS */
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#ifdef CONFIG_NVGPU_INJECT_HWERR
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void gv11b_ltc_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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u32 ltc = (error_info & 0xFF00U) >> 8U;
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u32 lts = (error_info & 0xFFU);
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u32 reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
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nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc, ltc_stride),
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nvgpu_safe_mult_u32(lts, lts_stride)));
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nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d",
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err->name, ltc, lts);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_r(void)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_r();
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(u32 v)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(v);
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(u32 v)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(v);
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}
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static struct nvgpu_hw_err_inject_info ltc_ecc_err_desc[] = {
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NVGPU_ECC_ERR("cache_rstg_ecc_corrected",
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gv11b_ltc_inject_ecc_error,
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ltc0_lts0_l1_cache_ecc_control_r,
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ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f),
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NVGPU_ECC_ERR("cache_rstg_ecc_uncorrected",
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gv11b_ltc_inject_ecc_error,
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ltc0_lts0_l1_cache_ecc_control_r,
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ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc ltc_err_desc;
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struct nvgpu_hw_err_inject_info_desc *gv11b_ltc_get_err_desc(struct gk20a *g)
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{
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ltc_err_desc.info_ptr = ltc_ecc_err_desc;
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ltc_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(ltc_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return <c_err_desc;
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}
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#endif /* CONFIG_NVGPU_INJECT_HWERR */
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