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git://nv-tegra.nvidia.com/linux-nvgpu.git
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7a8b12ab63
Install one completion fd per SET request. Notifications on dedicated event fd. Changed frequencies unit to Hz from MHz. Remove sequence numbers from dummy arbiter. Added effective clock type (query frequency from counters). Jira DNVGPU-125 Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1230239 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560) Reviewed-on: http://git-master/r/1243106
96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "clk/clk_arb.h"
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#include "clk_arb_gp106.h"
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static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
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{
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(void)g;
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return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
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}
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static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u64 *min_hz, u64 *max_hz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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struct clk_set_info *p5_info;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p5_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P5, clkwhich);
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if (!p5_info)
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return -EINVAL;
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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*min_hz = (u64)(p5_info->min_mhz) * (u64)MHZ;
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*max_hz = (u64)(p0_info->max_mhz) * (u64)MHZ;
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return 0;
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}
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static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
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u64 *default_hz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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*default_hz = (u64)p0_info->max_mhz * (u64)MHZ;
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return 0;
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}
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void gp106_init_clk_arb_ops(struct gpu_ops *gops)
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{
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gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains;
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gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range;
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gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default;
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}
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