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2dfa05ba50
- correct user register base l->usermode_regs. It should be bar0 address plus .usermode.bus_base(). .bus_base() returns user register base offset relative to bar0. - correct .usermode.base for tu104. .base should be user register base relative to virtual function base. - use nvgpu_usermode_writel for tu104 ring doorbell. Jira GVSCI-4650 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: Iba98063c4a5cc007459319b0311e546ff10604a4 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2403813 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/types.h>
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#include "os_linux.h"
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/*
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* Locks out the driver from accessing GPU registers. This prevents access to
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* thse registers after the GPU has been clock or power gated. This should help
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* find annoying bugs where register reads and writes are silently dropped
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* after the GPU has been turned off. On older chips these reads and writes can
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* also lock the entire CPU up.
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*/
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void nvgpu_lockout_usermode_registers(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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l->usermode_regs = NULL;
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}
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/*
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* Undoes t19x_lockout_registers().
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*/
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void nvgpu_restore_usermode_registers(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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l->usermode_regs = l->usermode_regs_saved;
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}
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void nvgpu_remove_usermode_support(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (l->usermode_regs) {
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l->usermode_regs = NULL;
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}
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}
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void nvgpu_init_usermode_support(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (g->ops.usermode.base == NULL) {
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return;
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}
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if (l->usermode_regs == NULL) {
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l->usermode_regs = l->regs + g->ops.usermode.bus_base(g);
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l->usermode_regs_saved = l->usermode_regs;
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}
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l->usermode_regs_bus_addr = l->regs_bus_addr +
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g->ops.usermode.bus_base(g);
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}
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