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MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite expressions. Resolve these violations by casting variables/constants to the appropriate types. Jira NVGPU-850 Jira NVGPU-853 Jira NVGPU-851 Change-Id: If6db312187211bc428cf465929082118565dacf4 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1931156 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
1.9 KiB
C
46 lines
1.9 KiB
C
/*
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* GM20B FUSE
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FUSE_GM20B_H
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#define NVGPU_FUSE_GM20B_H
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#define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK BIT32(0)
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#define GCPLEX_CONFIG_VPR_ENABLED_MASK BIT32(1)
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#define GCPLEX_CONFIG_WPR_ENABLED_MASK BIT32(2)
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struct gk20a;
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int gm20b_fuse_check_priv_security(struct gk20a *g);
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u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
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u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
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u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
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u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
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u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
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void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
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u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
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u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g);
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#endif /* NVGPU_FUSE_GM20B_H */
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