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de3ff22726
LSF loader cleanup, on gm20b/gp10b PMU falcon & other GR falcons uses different struct to store loader config which needs different functions to fill LSF loader config data, but on gv11b/gv10x/tu10a uses common falcon struct to store loader config, so made single function to fill LSF loader config data using ACR LSF struct & removed duplicate code. Removed ACR LSF loader ops which were part of PMU ops to cleanup dependency JIRA NVGPU-1148 Change-Id: I681829e05463d2517a4049433d8b0de3adeb06d9 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012853 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
66 lines
2.9 KiB
C
66 lines
2.9 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ACR_GP106_H
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#define NVGPU_ACR_GP106_H
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int gp106_bootstrap_hs_flcn(struct gk20a *g);
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int gp106_prepare_ucode_blob(struct gk20a *g);
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int gp106_alloc_blob_space(struct gk20a *g,
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size_t size, struct nvgpu_mem *mem);
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void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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void lsfm_free_ucode_img_res(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int lsf_gen_wpr_requirements(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm);
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void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm);
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void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
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u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode);
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int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
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int fecs_ucode_details(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int gpccs_ucode_details(struct gk20a *g,
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struct flcn_ucode_img_v1 *p_img);
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int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
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int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
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struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
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int lsfm_discover_ucode_images(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm);
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void lsfm_init_wpr_contents(struct gk20a *g,
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struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode);
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int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
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struct lsfm_managed_ucode_img_v2 *pnode);
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int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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u32 *acr_ucode_header);
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int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc, bool is_recovery);
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void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /* NVGPU_ACR_GP106_H */
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