Files
linux-nvgpu/drivers/gpu/nvgpu/common/sec2
Scott Long d5f26aa074 gpu: nvgpu: MISRA 10.1 fixes to pmu/sec2
MISRA Rule 10.1 states that operands shall not be of an
inappropriate essential type.

For example, the use of bitwise OR on signed values is not
permitted.

Both the pmu_read_message() and sec2_read_message() routines
do this in some cases when an error (or unexpected number of
bytes) is returned from the falcon queue pop/rewind routines.

This patch eliminates the MISRA violations by modifying these
cases to return the falcon queue operation error unmodified in the
corresponding status argument (or use -EINVAL in the event the
requested number of bytes isn't returned).

To reduce code duplication new pmu_falcon_queue_read() and
sec2_falcon_queue_read() routines are added here to wrap the
code that handles the error for the respective units.

Note that higher up in the call sequence (tu104_sec2_isr() in the
sec2_read_message() case and gk20a_pmu_isr() in the pmu_read_message()
case) the actual status value is only checked for non-zero or ignored
altogether.  So it appears no existing code would depend on the
bitwise OR result anyway.

JIRA NVGPU-650

Change-Id: Id303523ac096f1989e612044082e0a62ae8179c2
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972624
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-12-21 13:24:10 -08:00
..