mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
0a2bac5974
Remove WAR to set FMODEL during gv11b_init_hal. Instead, add io callbacks for tegra fuses, and return GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0. Jira NVGPU-3476 Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2120680 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
|
|
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
#include <nvgpu/fuse.h>
|
|
|
|
#include <os/posix/os_posix.h>
|
|
|
|
#include <nvgpu/posix/io.h>
|
|
#include <nvgpu/posix/soc_fuse.h>
|
|
|
|
int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
|
|
* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
|
|
*/
|
|
void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL ||
|
|
p->callbacks->tegra_fuse_control_write == NULL) {
|
|
return;
|
|
}
|
|
p->callbacks->tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL ||
|
|
p->callbacks->tegra_fuse_control_write == NULL) {
|
|
return;
|
|
}
|
|
|
|
p->callbacks->tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL || p->callbacks->tegra_fuse_writel == NULL) {
|
|
return;
|
|
}
|
|
|
|
p->callbacks->tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL || p->callbacks->tegra_fuse_writel == NULL) {
|
|
return;
|
|
}
|
|
|
|
return p->callbacks->tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
|
|
}
|
|
|
|
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL || p->callbacks->tegra_fuse_readl == NULL) {
|
|
return 0;
|
|
}
|
|
|
|
return p->callbacks->tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
|
|
}
|
|
|
|
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
|
|
{
|
|
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
|
|
|
|
if (p->callbacks == NULL || p->callbacks->tegra_fuse_readl == NULL) {
|
|
return -ENODEV;
|
|
}
|
|
|
|
return p->callbacks->tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
|
|
}
|