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QNX nvhost_syncpt_wait_timeout_ext() no longer supports reporting the current syncpoint value (which nvgpu does not use either). Jira HOSTX-1347 Change-Id: I5108f19a53802df63df014dd0ec3a103e0c6531f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2170180 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
214 lines
4.1 KiB
C
214 lines
4.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/nvhost.h>
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int nvgpu_get_nvhost_dev(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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void nvgpu_free_nvhost_dev(struct gk20a *g)
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{
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BUG();
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}
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int nvgpu_nvhost_module_busy_ext(
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struct nvgpu_nvhost_dev *nvhost_dev)
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{
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BUG();
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return 0;
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}
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void nvgpu_nvhost_module_idle_ext(
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struct nvgpu_nvhost_dev *nvhost_dev)
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{
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BUG();
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}
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void nvgpu_nvhost_debug_dump_device(
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struct nvgpu_nvhost_dev *nvhost_dev)
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{
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BUG();
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}
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const char *nvgpu_nvhost_syncpt_get_name(
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struct nvgpu_nvhost_dev *nvhost_dev, int id)
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{
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BUG();
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return NULL;
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}
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bool nvgpu_nvhost_syncpt_is_valid_pt_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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return false;
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}
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bool nvgpu_nvhost_syncpt_is_expired_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh)
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{
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BUG();
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return false;
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}
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u32 nvgpu_nvhost_syncpt_incr_max_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 incrs)
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{
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BUG();
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return 0U;
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}
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int nvgpu_nvhost_intr_register_notifier(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh,
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void (*callback)(void *priv, int nr_completed), void *private_data)
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{
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BUG();
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return 0;
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}
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void nvgpu_nvhost_syncpt_set_min_eq_max_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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void nvgpu_nvhost_syncpt_put_ref_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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u32 nvgpu_nvhost_get_syncpt_host_managed(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 param, const char *syncpt_name)
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{
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BUG();
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return 0U;
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}
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u32 nvgpu_nvhost_get_syncpt_client_managed(
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struct nvgpu_nvhost_dev *nvhost_dev,
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const char *syncpt_name)
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{
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BUG();
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return 0U;
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}
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int nvgpu_nvhost_syncpt_wait_timeout_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id,
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u32 thresh, u32 timeout)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvhost_syncpt_read_ext_check(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 *val)
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{
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BUG();
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return 0;
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}
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u32 nvgpu_nvhost_syncpt_read_maxval(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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return 0U;
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}
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void nvgpu_nvhost_syncpt_set_safe_state(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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int nvgpu_nvhost_create_symlink(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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void nvgpu_nvhost_remove_symlink(struct gk20a *g)
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{
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BUG();
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}
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#ifdef CONFIG_SYNC
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u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt)
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{
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BUG();
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return 0U;
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}
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u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt)
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{
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BUG();
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return 0U;
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}
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struct sync_fence *nvgpu_nvhost_sync_fdget(int fd)
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{
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BUG();
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return NULL;
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}
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int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence)
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{
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BUG();
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return 0;
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}
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struct sync_fence *nvgpu_nvhost_sync_create_fence(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh, const char *name)
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{
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BUG();
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return NULL;
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}
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#endif /* CONFIG_SYNC */
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#ifdef CONFIG_TEGRA_T19X_GRHOST
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int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size)
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{
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BUG();
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return 0;
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}
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u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
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{
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BUG();
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return 0U;
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}
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int nvgpu_nvhost_syncpt_init(struct gk20a *g)
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{
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return -ENOSYS;
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}
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#endif
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