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6c2c4181ae
There are many miscellaneous HALs for various MM related functionality. This patch aims to migrate all the remaining MM code from the <chip>/ mm_<chip>.[ch] files in HAL files under hal/. Much of this is fairly straightforward copy/paste and updates to the HAL init files. The exception to that is the move of the left over gv11b MMU fault handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in a subsequent patch. JIRA NVGPU-2042 Change-Id: I12896de865d890a61afbcb71159cff486119ffb8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
1.9 KiB
C
53 lines
1.9 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/mm.h>
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#include "mm_gv11b.h"
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void gv11b_mm_init_inst_block(struct nvgpu_mem *inst_block,
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struct vm_gk20a *vm, u32 big_page_size)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
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nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
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nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
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g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
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if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
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g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
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}
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if (g->ops.ramin.init_subctx_pdb != NULL) {
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g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false);
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}
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}
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bool gv11b_mm_is_bar1_supported(struct gk20a *g)
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{
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return false;
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}
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