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3c3f80a687
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in nvgpu by renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809082 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_VOLT_POLICY_H
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#define NVGPU_VOLT_POLICY_H
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#define VOLT_POLICY_INDEX_IS_VALID(pvolt, policy_idx) \
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(boardobjgrp_idxisvalid( \
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&((pvolt)->volt_policy_metadata.volt_policies.super), \
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(policy_idx)))
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/*!
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* extends boardobj providing attributes common to all voltage_policies.
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*/
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struct voltage_policy {
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struct boardobj super;
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};
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struct voltage_policy_metadata {
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u8 perf_core_vf_seq_policy_idx;
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struct boardobjgrp_e32 volt_policies;
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};
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/*!
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* extends voltage_policy providing attributes
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* common to all voltage_policy_split_rail.
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*/
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struct voltage_policy_split_rail {
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struct voltage_policy super;
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u8 rail_idx_master;
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u8 rail_idx_slave;
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u8 delta_min_vfe_equ_idx;
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u8 delta_max_vfe_equ_idx;
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s32 offset_delta_min_uv;
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s32 offset_delta_max_uv;
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};
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struct voltage_policy_split_rail_single_step {
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struct voltage_policy_split_rail super;
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};
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struct voltage_policy_split_rail_multi_step {
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struct voltage_policy_split_rail super;
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u16 inter_switch_delay_us;
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};
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struct voltage_policy_single_rail {
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struct voltage_policy super;
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u8 rail_idx;
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};
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struct voltage_policy_single_rail_multi_step {
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struct voltage_policy_single_rail super;
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u16 inter_switch_delay_us;
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u32 ramp_up_step_size_uv;
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u32 ramp_down_step_size_uv;
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};
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int volt_policy_sw_setup(struct gk20a *g);
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int volt_policy_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_VOLT_POLICY_H */
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