mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
ac98827c9d
LTC register write is followed by a register read and if data doesn't match code will report the error. Renamed existing nvgpu_writel_check function as nvgpu_writel_loop as it loops until the write get success. nvgpu_writel_check function write and read back and compare the data. Bug 2039150 Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762344 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
131 lines
3.0 KiB
C
131 lines
3.0 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/types.h>
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#include "os_linux.h"
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#include "gk20a/gk20a.h"
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void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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nvgpu_wmb();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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}
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void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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}
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}
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u32 nvgpu_readl(struct gk20a *g, u32 r)
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{
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u32 v = __nvgpu_readl(g, r);
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if (v == 0xffffffff)
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__nvgpu_check_gpu_state(g);
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return v;
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}
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u32 __nvgpu_readl(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->regs)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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v = readl(l->regs + r);
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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return v;
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}
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void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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nvgpu_wmb();
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do {
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writel_relaxed(v, l->regs + r);
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} while (readl(l->regs + r) != v);
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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}
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void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->bar1)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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nvgpu_wmb();
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writel_relaxed(v, l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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}
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u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->bar1)) {
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__gk20a_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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v = readl(l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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return v;
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}
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bool nvgpu_io_exists(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return l->regs != NULL;
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}
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bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return r < resource_size(l->regs);
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}
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