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git://nv-tegra.nvidia.com/linux-nvgpu.git
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124cdb4509
Renamed - gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave Moved set_interleave from runlist to tsg - runlist.set_interleave -> tsg.set_interleave Existing HAL was only setting tsg->interleave, and was not accessing any register. This is now done in nvgpu_tsg_set_interleave and tsg.set_interleave is only used in vgpu case. Jira NVGPU-3156 Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2100610 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
3.2 KiB
C
70 lines
3.2 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_VGPU_H
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#define NVGPU_FIFO_VGPU_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct tsg_gk20a;
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struct tegra_vgpu_fifo_intr_info;
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struct tegra_vgpu_channel_event_info;
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struct tegra_vgpu_channel_set_error_notifier;
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int vgpu_fifo_setup_sw(struct gk20a *g);
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void vgpu_fifo_cleanup_sw(struct gk20a *g);
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int vgpu_init_fifo_setup_hw(struct gk20a *g);
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void vgpu_channel_bind(struct channel_gk20a *ch);
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void vgpu_channel_unbind(struct channel_gk20a *ch);
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int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_enable(struct channel_gk20a *ch);
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void vgpu_channel_disable(struct channel_gk20a *ch);
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u32 vgpu_channel_count(struct gk20a *g);
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int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
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int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
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int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
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int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
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int vgpu_tsg_force_reset_ch(struct channel_gk20a *ch,
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u32 err_code, bool verbose);
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u32 vgpu_tsg_default_timeslice_us(struct gk20a *g);
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int vgpu_tsg_open(struct tsg_gk20a *tsg);
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void vgpu_tsg_release(struct tsg_gk20a *tsg);
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int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch);
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int vgpu_tsg_unbind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch);
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int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
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int vgpu_tsg_set_interleave(struct tsg_gk20a *tsg, u32 level);
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void vgpu_tsg_enable(struct tsg_gk20a *tsg);
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int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask);
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void vgpu_channel_free_ctx_header(struct channel_gk20a *c);
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int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
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void vgpu_handle_channel_event(struct gk20a *g,
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struct tegra_vgpu_channel_event_info *info);
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void vgpu_channel_abort_cleanup(struct gk20a *g, u32 chid);
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void vgpu_set_error_notifier(struct gk20a *g,
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struct tegra_vgpu_channel_set_error_notifier *p);
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#endif /* NVGPU_FIFO_VGPU_H */
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