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git://nv-tegra.nvidia.com/linux-nvgpu.git
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ef2a2be44f
This is adding compression support for Ampere gpus by the given contig memory pool. Bug 3426194 Change-Id: I1c2400094296eb5448fe18f76d021a10c33ef861 Signed-off-by: Dinesh T <dt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673581 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/dt.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_ivm.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/soc.h>
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#ifdef __KERNEL__
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#include <linux/tegra-ivc.h>
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#else
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#include <tegra-ivc.h>
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#endif
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#include <nvgpu/nvgpu_sgt.h>
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static void nvgpu_init_cbc_contig_pa(struct nvgpu_contig_cbcmempool *contig_pool)
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{
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contig_pool->base_addr = nvgpu_get_pa_from_ipa(contig_pool->g,
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contig_pool->cookie->ipa);
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contig_pool->size = contig_pool->cookie->size;
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}
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int nvgpu_cbc_contig_init(struct gk20a *g)
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{
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struct nvgpu_contig_cbcmempool *contig_pool;
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u32 mempool_id;
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int err;
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contig_pool = nvgpu_kzalloc(g, sizeof(*contig_pool));
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if (!contig_pool) {
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, false);
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return -ENOMEM;
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}
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contig_pool->g = g;
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nvgpu_mutex_init(&contig_pool->contigmem_mutex);
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g->cbc->cbc_contig_mempool = contig_pool;
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err = nvgpu_dt_read_u32_index(g, "phys_contiguous_mempool",
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0, &mempool_id);
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if (err) {
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nvgpu_err(g, "Reading the contig_mempool from dt failed %d", err);
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goto fail;
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}
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contig_pool->cookie = nvgpu_ivm_mempool_reserve(mempool_id);
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if (contig_pool->cookie == NULL) {
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nvgpu_err(g,
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"mempool %u reserve failed", mempool_id);
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contig_pool->cookie = NULL;
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goto fail;
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}
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contig_pool->cbc_cpuva = nvgpu_ivm_mempool_map(contig_pool->cookie);
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if (contig_pool->cbc_cpuva == NULL) {
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nvgpu_err(g, "nvgpu_ivm_mempool_map failed");
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goto fail;
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}
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nvgpu_init_cbc_contig_pa(contig_pool);
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return 0;
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fail:
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nvgpu_cbc_contig_deinit(g);
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err = -ENOMEM;
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, false);
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return err;
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}
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void nvgpu_cbc_contig_deinit(struct gk20a *g)
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{
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struct nvgpu_contig_cbcmempool *contig_pool;
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struct nvgpu_mem *mem;
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if ((g->cbc == NULL) || (g->cbc->cbc_contig_mempool == NULL)) {
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return;
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}
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contig_pool = g->cbc->cbc_contig_mempool;
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if (contig_pool->cookie != NULL &&
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contig_pool->cbc_cpuva != NULL) {
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nvgpu_ivm_mempool_unmap(contig_pool->cookie,
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contig_pool->cbc_cpuva);
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}
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if (contig_pool->cookie) {
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nvgpu_ivm_mempool_unreserve(contig_pool->cookie);
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}
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nvgpu_kfree(g, contig_pool);
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g->cbc->cbc_contig_mempool = NULL;
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mem = &g->cbc->compbit_store.mem;
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nvgpu_kfree(g, mem->phys_sgt->sgl);
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nvgpu_kfree(g, mem->phys_sgt);
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(void) memset(&g->cbc->compbit_store, 0,
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sizeof(struct compbit_store_desc));
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}
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