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6e4c3275bf
This is setting evict_max_ways for L2 cache to the maximum supported value for safety. In normal build L2 cache MAX_EVICT_LAST is configure via KMD and RegOps. RegOps is enabled only on standard build with CONFIG_DEBUGGER flag. This method we cant use it for safety build. Safety we can make use of the patch buffer to patch the register while creating the context. JIRA NVGPU-8227 Change-Id: Iec5d73197239b9cad31c6b593ca2b87c224aad5e Signed-off-by: Dinesh T <dt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2708702 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
/*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef LTC_GA10B_H
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#define LTC_GA10B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_gr_ctx;
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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u32 ga10b_ltc_zbc_table_size(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
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u32 index);
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void ga10b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index);
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void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index);
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#endif
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void ga10b_ltc_init_fs_state(struct gk20a *g);
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int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g);
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u64 ga10b_determine_L2_size_bytes(struct gk20a *g);
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int ga10b_lts_ecc_init(struct gk20a *g);
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#ifndef CONFIG_NVGPU_NON_FUSA
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void ga10b_set_default_l2_max_ways_evict_last(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx);
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr);
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int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
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u32 num_ways);
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int ga10b_get_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
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u32 *num_ways);
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#endif
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#endif /* LTC_GA10B_H */
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