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Implement the basic code to swap between PCIe bus speeds for the GPU. Other GPUs are not supported yet. Currently the following speeds can be used: Gen1 (2.5 MTPS) Gen2 (5.0 MTPS) gp106 on DPX2 does not support Gen3. JIRA DNVGPU-89 Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499 Reviewed-on: http://git-master/r/1218177 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1227925 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
138 lines
4.0 KiB
C
138 lines
4.0 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_xp_gp106_h_
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#define _hw_xp_gp106_h_
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static inline u32 xp_dl_mgr_r(u32 i)
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{
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return 0x0008b8c0 + i*4;
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}
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static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
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{
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return (v & 0x1) << 2;
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}
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static inline u32 xp_pl_link_config_r(u32 i)
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{
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return 0x0008c040 + i*4;
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}
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static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
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{
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return (v & 0x1) << 4;
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}
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static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
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{
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return 0x00000000;
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}
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static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
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{
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return (v & 0xf) << 0;
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}
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static inline u32 xp_pl_link_config_ltssm_directive_m(void)
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{
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return 0xf << 0;
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}
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static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
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{
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return 0x00000000;
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}
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static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
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{
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return 0x00000001;
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}
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static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
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{
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return (v & 0x3) << 18;
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}
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static inline u32 xp_pl_link_config_max_link_rate_m(void)
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{
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return 0x3 << 18;
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}
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static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
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{
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return 0x00000002;
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}
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static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
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{
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return 0x00000001;
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}
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static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
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{
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return 0x00000000;
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}
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static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
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{
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return (v & 0x7) << 20;
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}
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static inline u32 xp_pl_link_config_target_tx_width_m(void)
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{
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return 0x7 << 20;
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}
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static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
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{
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return 0x00000007;
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}
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static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
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{
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return 0x00000006;
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}
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static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
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{
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return 0x00000005;
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}
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static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
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{
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return 0x00000004;
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}
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static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
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{
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return 0x00000000;
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}
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#endif
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