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17c581d755
The basic nvgpu_mem_sgl implementation provides support for OS specific scatter-gather list implementations by simply copying them node by node. This is inefficient, taking extra time and memory. This patch implements an nvgpu_mem_sgt struct to act as a header which is inserted at the front of any scatter- gather list implementation. This labels every struct with a set of ops which can be used to interact with the attached scatter gather list. Since nvgpu common code only has to interact with these function pointers, any sgl implementation can be used. Initialization only requires the allocation of a single struct, removing the need to copy or iterate through the sgl being converted. Jira NVGPU-186 Change-Id: I2994f804a4a4cc141b702e987e9081d8560ba2e8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1541426 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/page_allocator.h>
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#include <nvgpu/bug.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/mm_gk20a.h"
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#include "gk20a/pramin_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
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/* WARNING: returns pramin_window_lock taken, complement with pramin_exit() */
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u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem,
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struct nvgpu_sgt *sgt, void *sgl, u32 w)
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{
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u64 bufbase = nvgpu_sgt_get_phys(sgt, sgl);
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u64 addr = bufbase + w * sizeof(u32);
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u32 hi = (u32)((addr & ~(u64)0xfffff)
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>> bus_bar0_window_target_bar0_window_base_shift_v());
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u32 lo = (u32)(addr & 0xfffff);
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u32 win = nvgpu_aperture_mask(g, mem,
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bus_bar0_window_target_sys_mem_noncoherent_f(),
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bus_bar0_window_target_vid_mem_f()) |
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bus_bar0_window_base_f(hi);
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gk20a_dbg(gpu_dbg_mem,
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"0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)",
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hi, lo, mem, sgl, bufbase,
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bufbase + nvgpu_sgt_get_phys(sgt, sgl),
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nvgpu_sgt_get_length(sgt, sgl));
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WARN_ON(!bufbase);
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nvgpu_spinlock_acquire(&g->mm.pramin_window_lock);
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if (g->mm.pramin_window != win) {
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gk20a_writel(g, bus_bar0_window_r(), win);
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gk20a_readl(g, bus_bar0_window_r());
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g->mm.pramin_window = win;
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}
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return lo;
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}
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void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem,
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void *sgl)
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{
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gk20a_dbg(gpu_dbg_mem, "end for %p,%p", mem, sgl);
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nvgpu_spinlock_release(&g->mm.pramin_window_lock);
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}
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