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5f010177de
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8839ac99e87153637005e23b3013237f57275c54 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530982 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
52 lines
2.0 KiB
C
52 lines
2.0 KiB
C
/*
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* GM20B ACR
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __ACR_GM20B_H_
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#define __ACR_GM20B_H_
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#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
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#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
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#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin"
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#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin"
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#define GM20B_PMU_UCODE_SIG "pmu_sig.bin"
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
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bool gm20b_is_pmu_supported(struct gk20a *g);
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int prepare_ucode_blob(struct gk20a *g);
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int gm20b_bootstrap_hs_flcn(struct gk20a *g);
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bool gm20b_is_lazy_bootstrap(u32 falcon_id);
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bool gm20b_is_priv_load(u32 falcon_id);
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void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
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int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size);
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int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
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int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms);
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int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
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int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz);
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int gm20b_pmu_setup_sw(struct gk20a *g);
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int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
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int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
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int acr_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img,
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unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig,
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unsigned int *p_patch_loc,
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unsigned int *p_patch_ind);
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#endif /*__ACR_GM20B_H_*/
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