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2f712e2230
- Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL flcn_gp106.c/h under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
27 lines
946 B
C
27 lines
946 B
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SEC2_H_
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#define __SEC2_H_
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int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
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int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
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int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
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void *desc, u32 bl_sz);
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void init_pmu_setup_hw1(struct gk20a *g);
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int init_sec2_setup_hw1(struct gk20a *g,
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void *desc, u32 bl_sz);
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int gp106_sec2_reset(struct gk20a *g);
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#endif /*__SEC2_H_*/
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