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c4370d7def
Initialize following counters in context header for all legacy chips: ctxsw_prog_main_image_num_save_ops ctxsw_prog_main_image_num_restore_ops This was already present in the code but move to a function gk20a_gr_init_ctxsw_hdr_data, so that it can be re-used across chips. Additionally initialize following preemption related counters for gp10b onwards in context header: ctxsw_prog_main_image_num_wfi_save_ops ctxsw_prog_main_image_num_cta_save_ops ctxsw_prog_main_image_num_gfxp_save_ops ctxsw_prog_main_image_num_cilp_save_ops Bug 1958308 Change-Id: I0e45ec718a8f9ddb951b52c92137051b4f6a8c60 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1562654 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
162 lines
6.0 KiB
C
162 lines
6.0 KiB
C
/*
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* GP10B GPU GR
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVGPU_GR_GP10B_H_
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#define _NVGPU_GR_GP10B_H_
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#include "gk20a/mm_gk20a.h"
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struct gk20a;
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struct gr_gk20a_isr_data;
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struct channel_ctx_gk20a;
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struct zbc_entry;
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struct gr_ctx_desc;
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struct nvgpu_preemption_modes_rec;
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enum {
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PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
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PASCAL_A = 0xC097,
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PASCAL_COMPUTE_A = 0xC0C0,
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PASCAL_DMA_COPY_A = 0xC0B5,
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PASCAL_DMA_COPY_B = 0xC1B5,
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};
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
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#define NVC097_SET_RD_COALESCE 0x102c
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC0C0_SET_RD_COALESCE 0x0228
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int gr_gp10b_init_fs_state(struct gk20a *g);
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int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
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struct nvgpu_mem *mem);
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void gr_gp10b_create_sysfs(struct device *dev);
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int gr_gp10b_handle_fecs_error(struct gk20a *g,
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struct channel_gk20a *__ch,
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struct gr_gk20a_isr_data *isr_data);
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int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
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struct channel_gk20a *fault_ch);
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bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num);
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bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
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bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num);
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int gr_gp10b_handle_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm,
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bool *post_event, struct channel_gk20a *fault_ch,
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u32 *hww_global_esr);
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int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
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bool *post_event);
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int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
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struct channel_gk20a *c, bool patch);
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void gr_gp10b_commit_global_pagepool(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, u32 size, bool patch);
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int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *color_val, u32 index);
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int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *depth_val, u32 index);
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u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
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int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
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void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
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int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void gr_gp10b_cb_size_default(struct gk20a *g);
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void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
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void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
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int gr_gp10b_init_ctx_state(struct gk20a *g);
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int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
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struct gr_ctx_desc *gr_ctx,
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struct vm_gk20a *vm, u32 class,
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u32 graphics_preempt_mode,
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u32 compute_preempt_mode);
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int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
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struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
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u32 class,
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u32 flags);
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void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
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struct gr_ctx_desc *gr_ctx);
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void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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struct nvgpu_mem *mem);
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int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
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struct gk20a_debug_output *o);
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int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
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u32 expect_delay);
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void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, bool patch);
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void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, u64 size, bool patch);
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int gr_gp10b_load_smid_config(struct gk20a *g);
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void gr_gp10b_init_cyclestats(struct gk20a *g);
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void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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void gr_gp10b_get_access_map(struct gk20a *g,
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u32 **whitelist, int *num_entries);
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int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
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bool sm_debugger_attached, struct channel_gk20a *fault_ch,
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bool *early_exit, bool *ignore_debugger);
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u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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u32 get_ecc_override_val(struct gk20a *g);
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int gr_gp10b_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
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bool boost);
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void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
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struct gr_ctx_desc *gr_ctx);
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int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
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u32 graphics_preempt_mode,
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u32 compute_preempt_mode);
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int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
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struct nvgpu_preemption_modes_rec *preemption_modes_rec);
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int gp10b_gr_fuse_override(struct gk20a *g);
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int gr_gp10b_init_preemption_state(struct gk20a *g);
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void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
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struct nvgpu_mem *mem, u64 gpu_va);
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int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
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void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem);
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struct gr_t18x {
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struct {
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u32 preempt_image_size;
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bool force_preemption_gfxp;
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bool force_preemption_cilp;
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bool dump_ctxsw_stats_on_channel_close;
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} ctx_vars;
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u32 fecs_feature_override_ecc_val;
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int cilp_preempt_pending_chid;
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};
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struct gr_ctx_desc_t18x {
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struct nvgpu_mem preempt_ctxsw_buffer;
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struct nvgpu_mem spill_ctxsw_buffer;
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struct nvgpu_mem betacb_ctxsw_buffer;
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struct nvgpu_mem pagepool_ctxsw_buffer;
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u32 ctx_id;
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bool ctx_id_valid;
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bool cilp_preempt_pending;
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};
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#endif
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