mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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7d584bf868
hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
131 lines
3.3 KiB
C
131 lines
3.3 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/tegra_vgpu.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/channel_gk20a.h"
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#include "gk20a/platform_gk20a.h"
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#include "gk20a/tsg_gk20a.h"
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#include "vgpu.h"
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#include <nvgpu/bug.h>
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static int vgpu_tsg_open(struct tsg_gk20a *tsg)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_open_params *p =
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&msg.params.tsg_open;
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int err;
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gk20a_dbg_fn("");
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msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(tsg->g,
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"vgpu_tsg_open failed, tsgid %d", tsg->tsgid);
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}
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return err;
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}
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static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
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&msg.params.tsg_bind_unbind_channel;
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int err;
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gk20a_dbg_fn("");
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err = gk20a_tsg_bind_channel(tsg, ch);
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if (err)
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return err;
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msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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p->ch_handle = ch->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(tsg->g,
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"vgpu_tsg_bind_channel failed, ch %d tsgid %d",
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ch->chid, tsg->tsgid);
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gk20a_tsg_unbind_channel(ch);
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}
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return err;
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}
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static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
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&msg.params.tsg_bind_unbind_channel;
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int err;
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gk20a_dbg_fn("");
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err = gk20a_tsg_unbind_channel(ch);
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if (err)
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return err;
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msg.cmd = TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL;
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msg.handle = vgpu_get_handle(ch->g);
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p->ch_handle = ch->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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WARN_ON(err);
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return err;
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}
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static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
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{
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struct tegra_vgpu_cmd_msg msg = {0};
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struct tegra_vgpu_tsg_timeslice_params *p =
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&msg.params.tsg_timeslice;
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int err;
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gk20a_dbg_fn("");
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msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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p->timeslice_us = timeslice;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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WARN_ON(err);
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if (!err)
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tsg->timeslice_us = timeslice;
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return err;
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}
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void vgpu_init_tsg_ops(struct gpu_ops *gops)
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{
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gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel;
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gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel;
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gops->fifo.tsg_set_timeslice = vgpu_tsg_set_timeslice;
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gops->fifo.tsg_open = vgpu_tsg_open;
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}
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