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44a87d320e
FECS ucode introduces separate register lists for control registers, so that they can be restored separately from PM state. Added support for: - LIST_compressed_nv_perf_sys_control_ctx_regs - LIST_compressed_nv_perf_pma_control_ctx_regs - LIST_compressed_nv_perf_fbp_control_ctx_regs - LIST_compressed_nv_perf_gpc_control_ctx_regs Bug 200507276 Change-Id: Ifce398bcb298822f3a46cf372ef9610a46a8df0c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2193528 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>