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f187e0bf44
Moved the SM_MASK_TYPE variable from GR to TSG struct. SM error registers are context based. In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel code iterate the TSG associated with first channel and set the mask_type to that context. Bug 200412641 Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809322 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
148 lines
4.8 KiB
C
148 lines
4.8 KiB
C
/*
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* Tegra GK20A GPU Debugger Driver
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*
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* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef DBG_GPU_H
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#define DBG_GPU_H
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#include <nvgpu/cond.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/list.h>
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struct gk20a;
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struct channel_gk20a;
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struct dbg_session_gk20a;
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/* used by the interrupt handler to post events */
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void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch);
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struct channel_gk20a *
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nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s);
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struct dbg_gpu_session_events {
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struct nvgpu_cond wait_queue;
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bool events_enabled;
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int num_pending_events;
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};
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struct dbg_session_gk20a {
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/* dbg session id used for trace/prints */
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int id;
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/* profiler session, if any */
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bool is_profiler;
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/* has a valid profiler reservation */
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bool has_profiler_reservation;
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/* power enabled or disabled */
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bool is_pg_disabled;
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/* timeouts enabled or disabled */
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bool is_timeout_disabled;
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struct gk20a *g;
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/* list of bound channels, if any */
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struct nvgpu_list_node ch_list;
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struct nvgpu_mutex ch_list_lock;
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/* event support */
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struct dbg_gpu_session_events dbg_events;
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bool broadcast_stop_trigger;
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struct nvgpu_mutex ioctl_lock;
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};
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struct dbg_session_data {
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struct dbg_session_gk20a *dbg_s;
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struct nvgpu_list_node dbg_s_entry;
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};
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static inline struct dbg_session_data *
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dbg_session_data_from_dbg_s_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_data *)
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((uintptr_t)node - offsetof(struct dbg_session_data, dbg_s_entry));
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};
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struct dbg_session_channel_data {
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int channel_fd;
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int chid;
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struct nvgpu_list_node ch_entry;
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struct dbg_session_data *session_data;
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int (*unbind_single_channel)(struct dbg_session_gk20a *dbg_s,
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struct dbg_session_channel_data *ch_data);
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};
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static inline struct dbg_session_channel_data *
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dbg_session_channel_data_from_ch_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_channel_data *)
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((uintptr_t)node - offsetof(struct dbg_session_channel_data, ch_entry));
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};
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struct dbg_profiler_object_data {
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int session_id;
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u32 prof_handle;
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struct channel_gk20a *ch;
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bool has_reservation;
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struct nvgpu_list_node prof_obj_entry;
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};
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static inline struct dbg_profiler_object_data *
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dbg_profiler_object_data_from_prof_obj_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_profiler_object_data *)
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((uintptr_t)node - offsetof(struct dbg_profiler_object_data, prof_obj_entry));
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};
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bool gk20a_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch);
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int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch);
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int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
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bool nvgpu_check_and_set_global_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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bool nvgpu_check_and_set_context_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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void nvgpu_release_profiler_reservation(struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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int gk20a_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size);
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int gk20a_perfbuf_disable_locked(struct gk20a *g);
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void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s);
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u32 nvgpu_set_powergate_locked(struct dbg_session_gk20a *dbg_s,
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bool mode);
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/* PM Context Switch Mode */
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/*This mode says that the pms are not to be context switched. */
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#define NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000)
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/* This mode says that the pms in Mode-B are to be context switched */
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#define NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW (0x00000001)
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/* This mode says that the pms in Mode-E (stream out) are to be context switched. */
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#define NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW (0x00000002)
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#endif /* DBG_GPU_GK20A_H */
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