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c4ac750e98
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: I478be317d067a75cdc8cb7fe9577a66d06318a11 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813068 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* drivers/video/tegra/host/gk20a/fence_gk20a.h
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*
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* GK20A Fences
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GK20A_FENCE_GK20A_H
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#define NVGPU_GK20A_FENCE_GK20A_H
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#include <nvgpu/types.h>
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#include <nvgpu/kref.h>
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#include <nvgpu/os_fence.h>
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struct platform_device;
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struct nvgpu_semaphore;
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struct channel_gk20a;
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struct gk20a;
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struct nvgpu_os_fence;
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struct gk20a_fence_ops;
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struct gk20a_fence {
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struct gk20a *g;
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/* Valid for all fence types: */
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bool valid;
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struct nvgpu_ref ref;
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const struct gk20a_fence_ops *ops;
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struct nvgpu_os_fence os_fence;
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/* Valid for fences created from semaphores: */
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struct nvgpu_semaphore *semaphore;
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struct nvgpu_cond *semaphore_wq;
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/* Valid for fences created from syncpoints: */
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struct nvgpu_nvhost_dev *nvhost_dev;
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u32 syncpt_id;
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u32 syncpt_value;
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/* Valid for fences part of a pre-allocated fence pool */
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struct nvgpu_allocator *allocator;
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};
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/* Fences can be created from semaphores or syncpoint (id, value) pairs */
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int gk20a_fence_from_semaphore(
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struct gk20a_fence *fence_out,
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struct nvgpu_semaphore *semaphore,
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struct nvgpu_cond *semaphore_wq,
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struct nvgpu_os_fence os_fence);
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int gk20a_fence_from_syncpt(
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struct gk20a_fence *fence_out,
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 value,
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struct nvgpu_os_fence os_fence);
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int gk20a_alloc_fence_pool(
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struct channel_gk20a *c,
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unsigned int count);
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void gk20a_free_fence_pool(
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struct channel_gk20a *c);
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struct gk20a_fence *gk20a_alloc_fence(
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struct channel_gk20a *c);
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void gk20a_init_fence(struct gk20a_fence *f,
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const struct gk20a_fence_ops *ops,
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struct nvgpu_os_fence os_fence);
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/* Fence operations */
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void gk20a_fence_put(struct gk20a_fence *f);
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struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f);
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int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f,
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unsigned long timeout);
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bool gk20a_fence_is_expired(struct gk20a_fence *f);
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bool gk20a_fence_is_valid(struct gk20a_fence *f);
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int gk20a_fence_install_fd(struct gk20a_fence *f, int fd);
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#endif /* NVGPU_GK20A_FENCE_GK20A_H */
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