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2eface802a
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_mutex_init and improves related error handling. JIRA NVGPU-677 Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805598 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "gk20a/flcn_gk20a.h"
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#include "gp106/sec2_gp106.h"
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#include "gp106/flcn_gp106.h"
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#include <nvgpu/hw/gp106/hw_falcon_gp106.h>
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static void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
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&flcn->flcn_engine_dep_ops;
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switch (flcn->flcn_id) {
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case FALCON_ID_PMU:
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flcn_eng_dep_ops->reset_eng = nvgpu_pmu_reset;
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flcn_eng_dep_ops->queue_head = g->ops.pmu.pmu_queue_head;
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flcn_eng_dep_ops->queue_tail = g->ops.pmu.pmu_queue_tail;
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break;
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case FALCON_ID_SEC2:
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flcn_eng_dep_ops->reset_eng = gp106_sec2_reset;
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break;
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default:
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flcn_eng_dep_ops->reset_eng = NULL;
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break;
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}
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}
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static void gp106_falcon_ops(struct nvgpu_falcon *flcn)
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{
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gk20a_falcon_ops(flcn);
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gp106_falcon_engine_dependency_ops(flcn);
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}
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int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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int err = 0;
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switch (flcn->flcn_id) {
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case FALCON_ID_PMU:
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flcn->flcn_base = FALCON_PWR_BASE;
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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case FALCON_ID_SEC2:
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flcn->flcn_base = FALCON_SEC_BASE;
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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case FALCON_ID_FECS:
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flcn->flcn_base = FALCON_FECS_BASE;
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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case FALCON_ID_GPCCS:
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flcn->flcn_base = FALCON_GPCCS_BASE;
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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case FALCON_ID_NVDEC:
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flcn->flcn_base = FALCON_NVDEC_BASE;
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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default:
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flcn->is_falcon_supported = false;
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nvgpu_err(g, "Invalid flcn request");
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err = -ENODEV;
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break;
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}
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if (flcn->is_falcon_supported) {
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err = nvgpu_mutex_init(&flcn->copy_lock);
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if (err != 0) {
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nvgpu_err(g, "Error in copy_lock mutex initialization");
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} else {
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gp106_falcon_ops(flcn);
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}
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} else {
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nvgpu_info(g, "falcon 0x%x not supported on %s",
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flcn->flcn_id, g->name);
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}
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return err;
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}
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