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7f8226887c
This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "pwrdev.h"
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#include "pmgrpmu.h"
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int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val)
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{
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struct nv_pmu_pmgr_pwr_devices_query_payload payload;
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int status;
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status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
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if (status)
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nvgpu_err(g, "pmgr_pwr_devices_get_current_power failed %x",
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status);
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*val = payload.devices[0].powerm_w;
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return status;
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}
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int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val)
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{
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struct nv_pmu_pmgr_pwr_devices_query_payload payload;
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int status;
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status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
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if (status)
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nvgpu_err(g, "pmgr_pwr_devices_get_current failed %x",
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status);
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*val = payload.devices[0].currentm_a;
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return status;
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}
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int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val)
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{
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struct nv_pmu_pmgr_pwr_devices_query_payload payload;
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int status;
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status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
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if (status)
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nvgpu_err(g, "pmgr_pwr_devices_get_current_voltage failed %x",
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status);
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*val = payload.devices[0].voltageu_v;
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return status;
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}
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u32 pmgr_domain_sw_setup(struct gk20a *g)
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{
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u32 status;
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status = pmgr_device_sw_setup(g);
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if (status) {
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nvgpu_err(g,
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"error creating boardobjgrp for pmgr devices, status - 0x%x",
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status);
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goto exit;
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}
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status = pmgr_monitor_sw_setup(g);
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if (status) {
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nvgpu_err(g,
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"error creating boardobjgrp for pmgr monitor, status - 0x%x",
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status);
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goto exit;
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}
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status = pmgr_policy_sw_setup(g);
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if (status) {
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nvgpu_err(g,
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"error creating boardobjgrp for pmgr policy, status - 0x%x",
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status);
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goto exit;
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}
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exit:
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return status;
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}
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int pmgr_domain_pmu_setup(struct gk20a *g)
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{
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return pmgr_send_pmgr_tables_to_pmu(g);
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}
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