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852d77ffaf
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gp106 by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I2a2d94dd04f4ed7307b7579fccb9d23154cb4946 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808250 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
2.0 KiB
C
46 lines
2.0 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_GP106_H
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#define NVGPU_PMU_GP106_H
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#define gp106_dbg_pmu(g, fmt, arg...) \
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nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
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struct gk20a;
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bool gp106_is_pmu_supported(struct gk20a *g);
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u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
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u32 gp106_pmu_pg_engines_list(struct gk20a *g);
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int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id);
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bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id);
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bool gp106_is_lazy_bootstrap(u32 falcon_id);
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bool gp106_is_priv_load(u32 falcon_id);
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int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
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void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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bool gp106_pmu_is_engine_in_reset(struct gk20a *g);
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int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset);
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#endif /* NVGPU_PMU_GP106_H */
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