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dfe8e8c09f
Fix following misra violations in pmu ipc units: 1. Rule 10.4: msg->msg.init.msg_type was being set value from enum. converted corresponding value PMU_INIT_MSG_TYPE_PMU_INIT to u8. Other conversions from signed to unsigned. Conversion of the enum PMU_RC_MSG_TYPE_UNHANDLED_CMD to unsigned value. 2. Rule 10.6: casted msg->hdr.size to U32 wherever required. 3. Rule 10.7: same as above. 4. Rule 13.5: nvgpu_timeout_expired() has side-effects of updating the timer counts. Using it as first operand of && in if clause. 5. Rule 16.4: added non-empty default clause to switch. 6. Rule 17.7: return value of nvgpu_pmu_vidmem_surface_alloc, nvgpu_falcon_copy_to_dmem, nvgpu_pmu_lsfm_int_wpr_region, nvgpu_timeout_init, pmu_init_perfmon, pmu_handle_event, pmu_response_handle and memset is handled. 7. Rule 2.2: removed unnecessary initialization of local variable. JIRA NVGPU-3273 Change-Id: Ie5a53bcdf0d138cb02867a09dc42195449e146a0 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2112619 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>