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Add range value details for various os_utils functions. Jira NVGPU-6258 Change-Id: Ib930a24d2a4b8e98520d87fcc2f48bef81d26fbd Signed-off-by: prsethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480205 (cherry picked from commit 210e1dd5360d29cad1a432e8de48669d51de134c) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483388 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
215 lines
6.4 KiB
C
215 lines
6.4 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_IO_H
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#define NVGPU_IO_H
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#include <nvgpu/types.h>
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/**
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* @file
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*
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* Interface for mmio access.
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*/
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/* Legacy defines - should be removed once everybody uses nvgpu_* */
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#define gk20a_writel nvgpu_writel
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#define gk20a_readl nvgpu_readl
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#define gk20a_writel_check nvgpu_writel_check
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#define gk20a_bar1_writel nvgpu_bar1_writel
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#define gk20a_bar1_readl nvgpu_bar1_readl
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#define gk20a_io_exists nvgpu_io_exists
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#define gk20a_io_valid_reg nvgpu_io_valid_reg
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struct gk20a;
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/**
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* @brief Write a value to a GPU register with an ordering constraint.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
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* @param v [in] Value to write at the offset.
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*
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* Write a 32-bit value to register offset in GPU IO space with an
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* ordering constraint on memory operations.
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*
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* @return None.
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*/
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void nvgpu_writel(struct gk20a *g, u32 r, u32 v);
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#ifdef CONFIG_NVGPU_DGPU
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/**
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* @brief Write a value to GPU register without an ordering constraint.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* @param v [in] Value to write at the offset.
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*
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* Write a 32-bit value to register offset in GPU IO space without
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* an ordering constraint on memory operations. This function is
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* implemented by the OS layer.
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*
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* @return None.
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*/
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void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v);
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#endif
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/**
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* @brief Read a value from a GPU register.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
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*
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* Read a 32-bit value from register offset in GPU IO space. If all
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* the bits are set in the value read then check for gpu state validity.
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* Refer #nvgpu_check_gpu_state() for gpu state validity check.
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*
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* @return Value at the given register offset in GPU IO space.
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*/
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u32 nvgpu_readl(struct gk20a *g, u32 r);
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/**
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* @brief Read a value from a GPU register.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
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*
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* Read a 32-bit to register offset from a GPU IO space. nvgpu_readl() is
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* called from this function. This function is implemented by the OS layer.
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*
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* @return Value at the given register offset in GPU IO space.
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*/
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u32 nvgpu_readl_impl(struct gk20a *g, u32 r);
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/**
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* @brief Write validate to a GPU register.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* @param v [in] Value to write at the offset.
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*
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* Write a 32-bit value to register offset in GPU IO space and reads it
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* back. Check whether the write/read values match and logs the event on
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* a mismatch.
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*
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* @return None.
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*/
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void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v);
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#ifdef CONFIG_NVGPU_NON_FUSA
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/**
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* @brief Ensure write to a GPU register.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO space.
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* @param v [in] Value to write at the offset.
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*
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* This is a blocking call. It keeps on writing a 32-bit value to a GPU
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* register and reads it back until read/write values are not match.
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*
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* @return None.
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*/
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void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v);
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#endif
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/**
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* @brief Write a value to an already mapped bar1 io-region.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in io-region.
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* Range: 0 - TEGRA_GK20A_BAR1_SIZE.
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* @param v [in] Value to write at the offset.
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*
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* - Write a 32-bit value to register offset of region bar1.
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*
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* @return None.
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*/
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void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v);
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/**
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* @brief Read a value from an already mapped bar1 io-region.
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*
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* @param g [in] GPU super structure.
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* @param b [in] Register offset in io-region.
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* Range: 0 - TEGRA_GK20A_BAR1_SIZE.
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*
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* - Read a 32-bit value from a region bar1.
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*
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* @return Value at the given offset of the io-region.
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*/
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u32 nvgpu_bar1_readl(struct gk20a *g, u32 b);
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/**
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* @brief Check bar0 io-region is mapped or not
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*
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* @param g [in] GPU super structure.
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*
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* - io mapping exists if bar0 address is assigned to regs.
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*
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* @return TRUE if bar0 is mapped or else FALSE.
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*/
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bool nvgpu_io_exists(struct gk20a *g);
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/**
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* @brief Validate BAR0 io-mapped offset.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in io-region.
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* Range: 0 - TEGRA_GK20A_BAR0_SIZE.
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*
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* - BAR0 Offset is valid if it falls into BAR0 range.
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*
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* @return TRUE if bar0 offset is valid or else FALSE.
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*/
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bool nvgpu_io_valid_reg(struct gk20a *g, u32 r);
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/**
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* @brief Write value to register at phys offset.
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*
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* @param g [in] GPU super structure.
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* @param r [in] Register offset in GPU IO-space.
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* @param v [in] Value to write at the offset.
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*
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* - Write a 32-bit value at phys offset. Phys_offset can be retrieved using
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* gops.func.get_full_phys_offset().
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*
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* @return None.
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*/
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void nvgpu_func_writel(struct gk20a *g, u32 r, u32 v);
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/**
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* @brief Read value from register at phys offset.
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*
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* @param g [in] GPU super structure.
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* @param b [in] Register offset in GPU IO-space.
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*
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* - Read a 32-bit value from phys offset. Phys_offset can be retrieved using
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* gops.func.get_full_phys_offset().
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*
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* @return Value at the given offset.
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*/
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u32 nvgpu_func_readl(struct gk20a *g, u32 r);
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#endif /* NVGPU_IO_H */
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