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9bee2fe660
Move preallocation of priv cmdbuf metadata structs to the priv cmdbuf level and do it always, not only on deterministic channels. This makes job tracking simpler and loosens dependencies from jobs to cmdbuf internals. The underlying dma memory for the cmdbuf data has always been preallocated. Rename the priv cmdbuf functions to have a consistent prefix. Refactor the channel sync wait and incr ops to free any priv cmdbufs they allocate. They have been depending on the caller to free their resources even on error conditions, requiring the caller to know how they work. The error paths that could occur after a priv cmdbuf has been allocated have likely been wrong for a long time. Usually the cmdbuf queue allows allocating only from one end and freeing from only the other end, as that's natural with the hardware job queue. However, in error conditions the just recently allocated entries need to be put back. Improve the interface for this. [not part of the cherry-pick:] Delete the error prints about not enough priv cmd buffer space. That is not an error. When obeying the user-provided job sizes more strictly, momentarily running out of job tracking resources is possible when the job cleanup thread does not catch up quickly enough. In such a case the number of inflight jobs on the hardware could be less than the maximum, but the inflight job count that nvgpu sees via the consumed resources could reach the maximum. Also remove the wrong translation to -EINVAL from err from one call to nvgpu_priv_cmdbuf_alloc() - the -EAGAIN from the failed allocation is important. [not part of the cherry-pick: a bunch of MISRA mitigations.] Jira NVGPU-4548 Change-Id: I09d02bd44d50a5451500d09605f906d74009a8a4 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329657 (cherry picked from commit 25412412f31436688c6b45684886f7552075da83) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332506 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
83 lines
2.8 KiB
C
83 lines
2.8 KiB
C
/*
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* Nvgpu Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANNEL_SYNC_PRIV_H
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#define NVGPU_CHANNEL_SYNC_PRIV_H
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/*
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* These APIs are used for job synchronization that we know about in the
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* driver. If submits happen in userspace only, none of this will be needed and
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* won't be included. This is here just to double check for now.
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*/
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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#include <nvgpu/atomic.h>
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#include <nvgpu/types.h>
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struct priv_cmd_entry;
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struct nvgpu_fence_type;
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struct nvgpu_channel_sync_ops;
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/*
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* This struct is private and should not be used directly. Users should
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* instead use the public APIs starting with nvgpu_channel_sync_*
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*/
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struct nvgpu_channel_sync {
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nvgpu_atomic_t refcount;
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const struct nvgpu_channel_sync_ops *ops;
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};
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/*
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* This struct is private and should not be used directly. Users should
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* instead use the public APIs starting with nvgpu_channel_sync_*
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*/
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struct nvgpu_channel_sync_ops {
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int (*wait_fence_raw)(struct nvgpu_channel_sync *s, u32 id, u32 thresh,
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struct priv_cmd_entry **entry);
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int (*wait_fence_fd)(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry **entry, u32 max_wait_cmds);
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int (*incr)(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry **entry,
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struct nvgpu_fence_type *fence,
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bool need_sync_fence,
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bool register_irq);
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int (*incr_user)(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry **entry,
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struct nvgpu_fence_type *fence,
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bool wfi,
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bool need_sync_fence,
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bool register_irq);
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void (*set_min_eq_max)(struct nvgpu_channel_sync *s);
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void (*destroy)(struct nvgpu_channel_sync *s);
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};
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#endif /* CONFIG_NVGPU_KERNEL_MODE_SUBMIT */
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#endif /* NVGPU_CHANNEL_SYNC_PRIV_H */
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