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8fdf40a849
Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* GV11B fifo
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*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gp10b/fifo_gp10b.h"
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#include "hw_pbdma_gv11b.h"
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#include "fifo_gv11b.h"
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#include "hw_fifo_gv11b.h"
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#include "hw_ram_gv11b.h"
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#include "hw_ccsr_gv11b.h"
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static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
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{
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u32 runlist_entry_0 = ram_rl_entry_type_tsg_v();
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if (tsg->timeslice_timeout)
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runlist_entry_0 |=
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ram_rl_entry_tsg_timeslice_scale_f(tsg->timeslice_scale) |
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ram_rl_entry_tsg_timeslice_timeout_f(tsg->timeslice_timeout);
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else
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runlist_entry_0 |=
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ram_rl_entry_tsg_timeslice_scale_f(
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ram_rl_entry_tsg_timeslice_scale_3_v()) |
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ram_rl_entry_tsg_timeslice_timeout_f(
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ram_rl_entry_tsg_timeslice_timeout_128_v());
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runlist[0] = runlist_entry_0;
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runlist[1] = ram_rl_entry_tsg_length_f(tsg->num_active_channels);
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runlist[2] = ram_rl_entry_tsg_tsgid_f(tsg->tsgid);
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runlist[3] = 0;
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gk20a_dbg_info("gv11b tsg runlist [0] %x [1] %x [2] %x [3] %x\n",
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runlist[0], runlist[1], runlist[2], runlist[3]);
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}
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static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
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{
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struct gk20a *g = c->g;
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u32 addr_lo, addr_hi;
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u32 runlist_entry;
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/* Time being use 0 pbdma sequencer */
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runlist_entry = ram_rl_entry_type_channel_v() |
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ram_rl_entry_chan_runqueue_selector_f(0) |
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ram_rl_entry_chan_userd_target_f(
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ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) |
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ram_rl_entry_chan_inst_target_f(
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ram_rl_entry_chan_userd_target_sys_mem_ncoh_v());
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addr_lo = u64_lo32(c->userd_iova) >>
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ram_rl_entry_chan_userd_ptr_align_shift_v();
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addr_hi = u64_hi32(c->userd_iova);
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runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo);
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runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi);
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addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >>
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ram_rl_entry_chan_inst_ptr_align_shift_v();
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addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block));
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runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) |
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ram_rl_entry_chid_f(c->hw_chid);
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runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi);
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gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n",
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runlist[0], runlist[1], runlist[2], runlist[3]);
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}
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void gv11b_init_fifo(struct gpu_ops *gops)
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{
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gp10b_init_fifo(gops);
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gops->fifo.runlist_entry_size = ram_rl_entry_size_v;
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gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry;
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gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry;
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}
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