mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 10:34:43 +03:00
90f80a282e
This CL covers the following implementation, 1) Power Sensor Table parsing. 2) Power Topology Table parsing. 3) Add debugfs interface to get the current power(mW), current(mA) and voltage(uV) information from PMU. 4) Power Policy Table Parsing 5) Implement PMU boardobj interface for pmgr module. 6) Over current protection. JIRA DNVGPU-47 Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1217189 (cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6) Reviewed-on: http://git-master/r/1241953 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
115 lines
1.9 KiB
C
115 lines
1.9 KiB
C
/*
|
|
* general p state infrastructure
|
|
*
|
|
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*/
|
|
|
|
#include "gk20a/gk20a.h"
|
|
#include "clk/clk.h"
|
|
#include "perf/perf.h"
|
|
#include "pmgr/pmgr.h"
|
|
|
|
/*sw setup for pstate components*/
|
|
int gk20a_init_pstate_support(struct gk20a *g)
|
|
{
|
|
u32 err;
|
|
|
|
gk20a_dbg_fn("");
|
|
|
|
err = clk_vin_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_fll_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = vfe_var_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = vfe_equ_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_domain_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_vf_point_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_prog_sw_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = pmgr_domain_sw_setup(g);
|
|
return err;
|
|
}
|
|
|
|
/*sw setup for pstate components*/
|
|
int gk20a_init_pstate_pmu_support(struct gk20a *g)
|
|
{
|
|
u32 err;
|
|
|
|
gk20a_dbg_fn("");
|
|
|
|
err = vfe_var_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = vfe_equ_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_domain_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_prog_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_vin_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_fll_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_vf_point_pmu_setup(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_pmu_vin_load(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = perf_pmu_vfe_load(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_vf_point_cache(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_set_boot_fll_clk(g);
|
|
if (err)
|
|
return err;
|
|
|
|
err = pmgr_domain_pmu_setup(g);
|
|
return err;
|
|
}
|
|
|