Seshendra Gadagottu 9160bd29c3 gpu: nvgpu: gm20b: update whitelist reg list ...

Added gm20b whitelist register access list with following
zcull registers:
gr_pri_gpcs_setup_debug_z_gamut_offset
gr_pri_gpcs_zcull_ctx_debug

Access to these registers is required by 3d API drivers to write
zcull depth values less than 0.25

Bug 2757650

Change-Id: I8eae7b027831b6c61b144898476dcb83cbe09644
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274559
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2020-12-15 14:10:29 -06:00

..

gpu

gpu: nvgpu: gm20b: update whitelist reg list

2020-12-15 14:10:29 -06:00

Kconfig

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00