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943eb77b20
Add following PMU Hals: - get_pmu_msgq_head - set_pmu_msgq_head - set_pmu_new_instblk JIRA NVGPU-9758 Change-Id: Iba1e37a299309e0e31970a8fbdf248d662bd759b Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2906872 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*
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* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "pmu_tu104.h"
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#include <nvgpu/hw/tu104/hw_pwr_tu104.h>
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bool tu104_is_pmu_supported(struct gk20a *g)
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{
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#ifdef CONFIG_NVGPU_SIM
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/* PMU not supported in dGpu Simulation */
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return false;
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} else
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#endif
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{
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return true;
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}
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}
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u32 tu104_pmu_falcon_base_addr(void)
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{
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return pwr_falcon_irqsset_r();
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}
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u32 tu104_pmu_queue_head_r(u32 i)
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{
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return pwr_pmu_queue_head_r(i);
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}
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u32 tu104_pmu_queue_head__size_1_v(void)
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{
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return pwr_pmu_queue_head__size_1_v();
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}
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u32 tu104_pmu_queue_tail_r(u32 i)
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{
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return pwr_pmu_queue_tail_r(i);
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}
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u32 tu104_pmu_queue_tail__size_1_v(void)
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{
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return pwr_pmu_queue_tail__size_1_v();
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}
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u32 tu104_pmu_mutex__size_1_v(void)
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{
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return pwr_pmu_mutex__size_1_v();
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}
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void tu104_pmu_setup_apertures(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 inst_block_ptr;
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/* PMU TRANSCFG */
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/* setup apertures - virtual */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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pwr_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_noncoherent_sysmem_f());
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/* PMU Config */
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gk20a_writel(g, pwr_falcon_itfen_r(),
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gk20a_readl(g, pwr_falcon_itfen_r()) |
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pwr_falcon_itfen_ctxen_enable_f());
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inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block);
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g->ops.pmu.set_pmu_new_instblk(g,
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pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
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pwr_pmu_new_instblk_valid_f(1) |
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nvgpu_aperture_mask(g, &mm->pmu.inst_block,
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pwr_pmu_new_instblk_target_sys_ncoh_f(),
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pwr_pmu_new_instblk_target_sys_coh_f(),
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pwr_pmu_new_instblk_target_fb_f()));
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}
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